Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 201

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

Application Note
The Zilog Datacom Family with the 80186 CPU
(M)USC
Since
addresses and data, the (M)USC is configured to use the
addresses on the AD lines. Therefore, the software need
not write register addresses into the indirect address field
of the (M)USC’s CCAR.
The (M)USC’s Transmitter and Receiver can be handled
on a polled or interrupt-driven basis. In addition, any two of
the Receivers and Transmitters in the (M)USC and
Channel B of the (E)SCC can be handled on a DMA basis,
using the 80186’s integrated DMA controllers.
Jumper block J22 connects the (M)USC’s /RxREQ and
/TxREQ outputs to the “DMA EPLD” that makes the DMA
Requests to the 80186. As shipped from the factory,
jumpers are installed between J22-J1 and J22-J2, and
between J22-J3 and J22-J4. In this configuration, the
(M)USC’s /RxREQ drives the 80186 DREQ0, and (M)USC
/TxREQ drives the 80186 DREQ1. To reverse this
assignment, jumper J22-J1 to J22-J3 and J22-J2 to J22-
J4. To disconnect the (M)USC from one or both of the
80186’s DMA channels, remove one or both jumpers (put
them in a safe place in case you change your mind).
Jumper block J29 provides the same connection-variability
for the /RxREQ and /TxREQ outputs of Channel B of a
USC.
Since the 80186’s DMA channels are not capable of fly-by
operation, the (M)USC’s /RxACK and /TxACK pins have
no dedicated function. They can be used for Request to
Send and Data Terminal Ready; the two signals are lightly
pulled up since they are not driven after Reset.
The (M)USC can be programmed using 16-bit data on the
AD15-AD0 lines or 8-bit data on AD15-AD8 and AD7-AD0.
It makes the distinction between 8-bit and 16-bit
operations as part of its address map rather than through
a control input. The PS pin of an MUSC, or the A//B pin of
a USC, is connected to a latched version of 80186 A7. The
D//C pin of the (M)USC is grounded. The overall address
6-66
The fact that the ISCC’s internal logic sees activity on its
/AS pin, which is inverted from the 80186' ALE signal,
automatically
Address/Data bus.
(PBA)+128, 130, ..., (PBA)+190
(PBA)+192, 194, ..., (PBA)+222
(PBA)+224, 226, ..., (PBA)+254
the
80186
conditions
processor
it
provides
for
a
multiplexed
multiplexed
Given that the BCR is written as above, the ISCC’s slave-
mode address map is as follows:
range of the (M)USC is 256 bytes, between (PBA)+256
and (PBA)+511.
The first write to this address range, after a Reset,
implicitly writes the (M)USC’s Bus Configuration Register
(BCR). To match the rest of the board’s hardware, this first
write should be a 16-bit write, storing the hex value 0007
at any address in the second half of the (M)USC’s range
[any address in (PBA)+384 through 510, i.e., in the A
channel of a USC]. Details of this transaction are as
follows:
Given that the BCR is written as above, the (M)USC
address map is as follows:
The High on the PS or A//B input, which is connected to
A7, selects the WAIT protocol on the /WAIT//RDY pin,
corresponding to how the 80186 works.
The MSB of the data (D15) is 0 because a separate non-
multiplexed address is not wired to pins AD13:8 of the
(M)USC.
Bits 14-3 are required to be all zeros by the (M)USC’s
internal logic.
D2 of the data is 1 to tell the (M)USC that the data bus is
16 bits wide.
D1 of the data is 1 to select double-pulsed mode for the
(M)USC’s /INTACK input. This is how the 80186 works.
D0 of the data is 1 to select Shift Right Address mode so
that the (M)USC subsequently takes register addressing
from the AD6-AD0 lines rather than from AD7-AD1.
The fact that the (M)USC’s internal logic sees activity
on its /AS pin, which is inverted from the 80186' ALE
signal, automatically conditions it for a multiplexed
Address/Data bus.
DMA Controller Registers
ISCC Serial Channel B registers 0-15
ISCC Serial Channel A registers 0-15
UM010901-0601