Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 253

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

Application Note
Boost Your System Performance Using The Zilog ESCC
ESCC/SCC DIFFERENCES
The differences between the ESCC and SCC are shown
below:
1. Extended Read Enable of Write Registers
2. Hardware Improvement
3. Throughput improvement
4 SDLC End Of Frame Improvement
The differences between the ESCC and SCC are
summarized by a new register, WR7' (Figure 1).
6-118
- Modified WRITE Timing
- Modified DMA Request on
- Transmit Deactivation Timing
- Deeper Transmit FIFO
- Deeper Receive FIFO
- FIFO Interrupt Level
- Automatic RTS Deassertion after Closing Flag
- Automatic Opening Flag Transmission
- Automatic TxD Forced High in SDLC with NRZI Encoding
- Improvement to Allow Transmission of Back-to-Back
- Status FIFO Anti-Lock Feature in DMA-Driven System
RR7' Prime
When Marking Idle After End Of Frame
Frames with a Shared Flag
D7
Addressing:
WR15 D0
WR7
D6 D5 D4 D3 D2
Figure 1. WR7' Definition
'XX'
'1'
ESCC ENHANCEMENT
D1 D0
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivate
Rx FIFO Int Level
DTR/REQ Timing
Tx FIFO Int Level
Extended RD Enable
Not Used, Always 0
™
The advantages of the new features are illustrated in the
following examples.
One of the features that is offered by the ESCC, but not the
SCC, is Extended Read Enable. Write Register values
from the WR3, WR4, WR5, WR7', and WR10 can be
examined in the ESCC but not the SCC. This feature
improves system testability. It is also crucial for
SCC/ESCC differentiation and allows generic software
structures for all SCC/ESCC devices.
Flowchart 1 (Figure 2) shows a generic software structure
applicable for all SCC/ESCC initializations. Flowchart 2
(Figure 3) suggests a method for determining which type
of SCC/ESCC™ device is in the socket. This software
structure helps the development of software drivers
independent of the device type.
- Improves Testability
- Ability to examine SDLC status on-the-fly
- Improves Interface to 80X86 CPU
- Improves Interface DMA-driven system
- Reduces TBE Interrupt Frequency by 3/4
- Reduces RCA Interrupt Frequency by 3/4
- Flexibility in Adapting CPU Workload
- Reduces CPU and DMA Controller Overhead after
- Allows Optimal SDLC Line Utilization
End Of Frame
PERFORMANCE BENEFITS
UM010901-0601