Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 300

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
CONFIGURING THE BUS
The bus configuration programming is done in two
separate steps (actually it is one operation), to enable the
write to the Bus Configuration Register (BCR). The first
operation that accesses the ISCC after a device reset must
be a write to the BCR since this is the only time that the
BCR is accessible. Before and during the write, various
external signals are sampled to program bus configuration
parameters. During this write, the AØ/SCC//DMA pin must
be Low.
Address strobe programs multiplexed/non-multiplexed
selection. In a non-multiplexed bus environment, address
strobe (as an input) is not used but tied high through a
suitable pull-up resistor. Thus, no address strobe is
present before the BCR write. Then, when write to the
BCR
programmed because there is no address strobe before
this first write to the device. Note that address strobe
becomes an output during DMA operations so it is not tied
directly to V
During the write operation to the BCR, the A1/A/B input is
sampled to select the function of the WAIT/RDY pin (Table
A-2). When the BCR Write is to the SCC Channel A
(A1/A//B High during the BCR write), the WAIT/RDY signal
functions as a wait. When the BCR Write is to Channel B
(A1/A//B Low during the BCR write), the WAIT/RDY signal
functions as a ready.
This programming affects the function of the WAIT/RDY
signal both as an input, when the ISCC is bus master
during DMA operations, and as an output when the ISCC
is a bus slave.
With this programming, the ISCC is immediately
configured to function successfully on this first and
subsequent
configuration options are programmed by the value written
to the BCR.
Bit 0 of the BCR controls the Shift Left/Shift Right address
decoding modes for the DMA section. In this case, the shift
function is similar to the SCC section. During Left Shift, the
internal register addresses decode from bits AD5 through
AD1. During Right Shift, the internal register addresses
are decode from bits AD4 through AD0. This function is
only applicable in the multiplexed bus mode.
Table 40. Signals Sampled During the BCR Write
A1/A//B
takes
1
0
CC.
bus
place,
WAIT/RDY Function
WAIT (8086 RDY compatible)
READY (68000 DTACK compatible)
transactions.
the
non-multiplexed
The
remaining
mode
bus
is
Bits 1 and 2 of the BCR control the interrupt acknowledge
type as shown in the Table A-3.
The Status Acknowledge remains active throughout the
interrupt cycle and is directly compatible with the 680x0
family interrupt handshaking. The Status Acknowledge
signal latches with the rising edge of AS for multiplexed
bus operation. It latches by the falling edge of the strobe
(RD or DS) for non-multiplexed bus operation. The Pulsed
Acknowledges are timed to be active during a specified
period in the interrupt cycle. The Double Pulsed
Acknowledge is directly compatible with the 8x86 family
interrupt handshaking. Refer to the timing diagrams in the
ISCC Product Specification for details on the Acknowledge
signal operation.
Reserve bits 3, 4, and 5 of the BCR program as zeros. Bits
6 and 7 of the BCR control the byte swap feature (Table A-
4). Byte swap is applicable only in DMA transfers when the
ISCC is the bus master and only affects ISCC data
acceptance (transfers from memory to the ISCC).l
* BCR bit 6
Enable (BCR bit
BCR bit 2
Select*
Swap
Table 41. BCR Control of Interrupt Acknowledge
0
0
0
1
0
0
1
1
7)
0
1
Interfacing the ISCC™ to the 68000 and 8086
Table 42. Byte Swap Contro
BCR bit 1 Interrupt Acknowledge
A0
DMA Data Read by the ISCC
lower 8 bits of bus only
upper or lower 8 bits of bus
0
1
1
1
0
1
0
1
Status Acknowledge
Pulsed Acknowledge (single)
Reserved (action not defined)
Double Pulsed Acknowledge
DMA Data read by the ISCC
upper 8 bits of bus
lower 8 bits of bus
lower 8 bits of bus
upper 8 bits of bus
Application Note
6-5