Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 308

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
Asynchronous mode:
Synchronous mode:
Q. Can the maximum transfer rate using an external
A. Yes, but it is not trivial. In order to achieve the maximum
FIFO
Q. How do you avoid an overrun in the received
A. The receive buffer must be read before the recently re-
Q. What happens when you read an empty FIFO?
A. You read the last character in the buffer.
External clock
BRG
Using external clock
Using DPLL, FM encoding
Using DPLL, MRZ/NRZI encoding
Using DPLL, FM, BRG
Using DPLL, NRZ/NRZI, BRG
6x mode (no BRG)
16x mode (TX + 0)
FIFO?
clock be achieved?
rate on transmit, the SCC should have a dedicated pro-
cessor or DMA. For example, at a 1 MHz rate, a byte
must be loaded into the SCC every 8 microseconds. To
ceived data character on the serial input is shifted into
the receive data FIFO. This FIFO is three bytes deep.
Thus, if the buffer is not read, the fifth character just ar-
rived causes an overrun condition. There is no bit that
can be set or reset to disable the buffering.
4 MHz
32.25K
62.5K
62.5K
250K
250K
125K
1M
6 MHz
93.75K
187.5K
93.75K
46.88K
375K
375K
1.5M
Q. When the FIFO gets locked due to an error condi-
A. The SCC continues to receive until an overrun occurs.
Q. Assuming that there are characters available in
A. They will remain in the FIFO until they are either read
achieve the maximum rate on receive, requires that the
receive clock and the SCC PCLK be synchronized.
(RTxC to PCLK setup time at maximum rate in the
Product Specification.) It is probably easier to use a
slightly faster PCLK SCC, or back off slightly from the
maximum rate.
tion, can it still receive?
the FIFO, what happens to them if the receiver
goes into the hunt mode?
by the CPU or DMA, or until the channel is reset.
8 MHz
62.5K
500K
125K
500K
250K
125K
2M
10 MHz
156.25K
78.125K
156.5K
312.5K
635K
625K
2.5M
SCC™/ESCC™ User’s Manual
16 MHz
250K
500K
250K
125K
1M
4M
1M
20 MHz
Zilog SCC
156.25K
312.5K
312.5K
1.25M
1.25M
625K
5M
7-3