Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 230

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
Notes on Figure 1:
1. The SCC has two possible idle states, Mark idle
2. Transmit Buffer Empty Interrupt for 81H. At this point
3. The time between the first data byte being transferred
9. The transmitted CRC is 16 bits long provided that
10. The last interrupt generated occurs after the CRC is
(contiguous logic 1) or Flag idle (repeating flag pattern
7EH). In this figure, the SCC has to be switched to flag
idle in order to send the opening flag of the frame.
Care must be taken not to put the first data byte (in this
case, address 81H) into the Transmit Buffer too soon
after the switchover from Mark idle to Flag idle has
been made; otherwise, the data may be loaded into
the Transmit Shift Register before the flag is loaded.
To ensure that this cannot happen, a delay must be
executed before the first data byte is put into the
buffer. The delay time is dependent on the data rate
and a safe minimum duration is 8 bit-times.
the data has just been transferred to the Transmit Shift
Register and data 42H is written to the Transmit
Buffer.
to the Shift Register and the first bit appearing at the
TxD pin is always six bit-times.
there are no zero insertions. In theory it could be as
long as 19 bits.
shifted out of the transmitter and a flag is loaded to be
sent. It is a Transmit Buffer Empty Interrupt. If another
Abort/Flag on
Underrun bit
0
1
0
1
Tx Underrun/EOM Latch
State when Underrun occurs
Reset
Reset
Set
Set
Serial Communication Controller (SCC
4. Transmit Buffer Empty Interrupt for data 42H. Data
5. Transmit Buffer Empty Interrupt for data 0FFH. Data
6. The time between interrupts depends on the data
7. Transmit Buffer Empty Interrupt for data 42H. Since
8. Transmitter Underrun/EOM Interrupt. This occurs
11. If the SCC is set up for mark on idle and a new
0FFH is written to the Transmit Buffer at this point.
42H is written to the Transmit Buffer at this point.
character length and the number of zero insertions in
the character. For 8 bits/character it can vary between
8 and 10 bit-times. The particular instance shown
corresponds to the single zero insertion when the byte
0FFH is transmitted.
this is the last byte to be transmitted, the Reset
Transmit Interrupt Pending command is issued
instead of writing another byte to the Transmit Buffer.
when both the Transmit Shift Register and the
Transmit Buffer are empty. It is an External/Status
interrupt. The data sent when this occurs is
summarized in the table below:
frame is to be transmitted, the first character of the
next frame can be loaded. The two frames will then be
separated by a single flag (Back-to-back frame).
character is not loaded when the last interrupt occurs,
only a single flag is sent.
™
Data
Sent
CRC and Flag
Abort and Flag
Flags
Flags
): SDLC Mode of Operation
Application Note
6-95
1