Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 309

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

SCC™/ESCC™ User’s Manual
Zilog SCC
SPECIAL MODES
(LOCAL, LOOPBACK, DPLL, MANCHESTER)
Q How are the Local, Loopback, and Auto Echo
A. The TxD and RxD pins are connected through drivers.
Q. Can the SCC transmit when the Auto Echo mode is
A. No, the transmitter is logically disconnected from the
Q. Can the Digital Phase Lock Loop (DPLL) be used
A. The DPLL simply generates the receive clock which is
Q. Do you have to use the DPLL with NRZI and FM en-
A. If the DPLL is not used, a properly phased external
Q. What is the error tolerance for the DPLL?
A. The DPLL can only tolerate a + or - 1/32 deviation in
INTERNAL TIMING
Q. When does data transfer from the transmit buffer
A. About 3 PCLK’s after the last bit is shifted out.
Q. How long does it take for a write operation to get
A. It takes about 5 PCLK’s for the data to get to the buffer.
Q. What is Valid Access Recovery Time?
A. Since WR/ and RD/ (AS/ and DS/ on the Z8030) have
Q. How long is Valid Access Recovery Time?
A. On the NMOS SCC, the recovery time is 4 PCLK’s,
Q. Why does the Z8030 require that the PCLK be “at
A. If the clocks are within 90%, then the setup and hold
7-4
to the shift register?
to the transmit buffer?
least 90% of the CPU clock frequency for Z8000?“
modes implemented?
If both modes are simultaneously enabled, then Auto
Echo overrides.
enabled?
TxD pin.
with NRZ?
the same for both NRZ and NRZI.
coding?
clock must be supplied.
frequency, or about 3%.
no phase relationship with PCLK, the circuitry generat-
ing these internal control signals must provide time for
metastable conditions to disappear. This gives rise to
a recovery time related to PCLK.
while on the CMOS SCC, the recovery time is 3-3.5
PCLK’s.
times will be met. Otherwise, the setup and hold times
must be met by the user.
Q. Can you receive and transmit between two chan-
A. To transmit and receive using the same clock, you
Q. How fast will Manchester be decoded?
A. The SCC can decode Manchester data by using the
Q. When will the Time Constant be loaded into the
A. After a S/W reset or a Zero Count is reached.
Q. How to run NRZ data using the DPLL?
A. Use NRZI for DPLL (WR14) but set to NRZ (WR10).
Q. Does Valid Access Recovery Time apply to all suc-
A. Any access to the SCC requires that the recovery time
Q. Do the DMA request and wait lines on the SCC take
A. No, they are not that intelligent. The user must take
Q. What happens if Valid Access Recovery Time is
A. Invalid data can result.
nels on the same SCC using the DPLL to generate
both the transmit and receive clocks?
need to divide the transmit clock by 16 or 32 to be the
same rate for transmitting and receiving, because the
DPLL requires a divide-by-16 or -32 on the receiver,
depending on the encoding. An external divide-by-16
or -32 is required, and can be connected by outpouring
the bit rate generator on the /TRxC pin, through the ex-
ternal divide circuit, and back in the /RTxC pin as an
input to the transmitter.
DPLL in the FM mode and programming the receiver
for NRZ data. Hence, the 125K bit/s is the maximum
rate for decoding at 8MHz SCC. A circuit for encoding
Manchester is available from Zilog.
BRG counter?
cessive accesses to the SCC?
be observed before a new access. This includes read-
ing several bytes from the receive FIFO, accessing
separate bytes on two different channels, etc. When
using DMA or block transfer methods, the recovery
time must be considered.
the Valid Access Recovery time into account be-
fore they make a request?
this into account, and program the DMA accordingly.
For example, by inserting wait states during the mem-
ory access between SCC accesses, which will length-
en the time in between SCC accesses, or by requiring
the DMA to release the bus between accesses to the
SCC, to prevent simultaneous data requests from two
channels from violating the recovery time.
violated?
UM010901-0601