EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 95

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–75. Arria GX IOE in DDR Output I/O Configuration
Notes to
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port.
(3) The optional PCI clamp is only available on column I/O pins.
© December 2009 Altera Corporation
Figure
Column, Row,
Interconnect
or Local
2–75:
ioe_clk[7..0]
When using the IOE for DDR outputs, the two output registers are configured to clock
two data paths from ALMs on rising clock edges. These output registers are
multiplexed by the clock to drive the output pin at a ×2 rate. One output register
clocks the first bit out on the clock high time, while the other output register clocks the
second bit out on the clock low time.
output.
clkout
aclr/apreset
sclr/spreset
ce_out
oe
Figure 2–76
Chip-Wide Reset
shows the DDR output timing diagram.
Output Register
Output Register
OE Register
OE Register
ENA
Notes (1), (2)
CLRN/PRN
CLRN/PRN
CLRN/PRN
CLRN/PRN
D
ENA
D
ENA
D
ENA
D
Q
Q
Q
Q
Figure 2–75
Used for
DDR, DDR2
SDRAM
clk
Open-Drain Output
Drive Strength
Pin Delay
Output
Control
shows the IOE configured for DDR
OE Register
t CO Delay
V CCIO
Arria GX Device Handbook, Volume 1
V CCIO
PCI Clamp (3)
Termination
On-Chip
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
2–89