EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 70

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–64
Figure 2–53. DSP Block Interface to Interconnect
Arria GX Device Handbook, Volume 1
f
C4 Interconnect
LAB
A bus of 44 control signals feeds the entire DSP block. These signals include clocks,
asynchronous clears, clock enables, signed and unsigned control signals, addition and
subtraction control signals, rounding and saturation control signals, and accumulator
synchronous loads. The clock signals are routed from LAB row clocks and are
generated from specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in
For more information about DSP blocks, refer to the
chapter.
18
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
16
Row Interface
36
12
Block
36 Inputs per Row
R4 Interconnect
16
Control
A[17..0]
B[17..0]
DSP Block
Row Structure
OA[17..0]
OB[17..0]
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
DSP Blocks in Arria GX Devices
36
Table
© December 2009 Altera Corporation
2–15.
Chapter 2: Arria GX Architecture
Direct Link Interconnect
from Adjacent LAB
Digital Signal Processing Block
LAB