EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 199

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 4)
© December 2009 Altera Corporation
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
I/O Standard
Strength
10 mA
12 mA
16 mA
18 mA
20 mA
Drive
—
—
—
Table 4–76
that should be added to the GCLK values. These adder values are used to determine
I/O timing when the I/O pin is driven using the regional clock. This applies for all
I/O standards supported by Arria GX with general purpose I/O pins.
Table 4–76
devices.
Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
GCLK PLL
Parameter
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
through
lists row pin delay adders when using the regional clock in Arria GX
Table 4–77
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
Industrial
list the EP1AGX90 regional clock (RCLK) adder values
–0.175
–0.007
0.175
0.007
Industrial
2.845
0.783
2.839
0.777
2.826
0.764
2.829
0.767
2.831
0.769
2.987
0.923
2.987
0.923
3.835
1.769
Fast Corner
Fast Corner
Commercial
Commercial
–0.175
–0.007
0.175
0.007
2.845
0.783
2.839
0.777
2.826
0.764
2.829
0.767
2.831
0.769
2.987
0.923
2.987
0.923
3.835
1.769
Arria GX Device Handbook, Volume 1
–6 Speed Grade
–6 Speed
Grade
6.264
2.133
6.262
2.131
6.074
1.943
6.084
1.953
6.097
1.966
6.414
2.279
6.414
2.279
7.541
3.404
–0.418
–0.015
0.418
0.015
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
4–77