EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 223

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
Table 4–114. High-Speed Timing Specifications and Definitions (Part 2 of 2)
Table 4–115. High-Speed I/O Specifications (Part 1 of
© December 2009 Altera Corporation
Timing unit interval (TUI)
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t
t
f
f
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
High-Speed Timing Specifications
H S D R
H S D R D PA
D U T Y
L O CK
H S C L K
H S C L K
H S D R
H S D R D PA
D U T Y
(data rate)
(clock frequency)
= f
R I SE
F AL L
Symbol
(DPA data rate)
H S D R
/ W
Table 4–115
W = 2 to 32 (LVDS, HyperTransport technology)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
All differential I/O standards
All differential I/O standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
—
shows the high-speed I/O timing specifications.
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = t
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges, including t
variation and clock skew. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture it
correctly. The setup and hold times determine the ideal strobe position within the
sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Conditions
—
—
2)Note (1), (2)
Definitions
(3)
0.44
Min
150
150
150
440
16
16
(4)
(4)
—
—
—
—
45
—
H S D R
H S D R D P A
–6 Speed Grade
= 1/TUI), non-DPA.
= 1/TUI), DPA.
Typ
Arria GX Device Handbook, Volume 1
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
6,400
Max
420
500
640
840
700
500
840
200
190
290
290
—
55
—
C
/w).
Mbps
Mbps
Mbps
Mbps
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
UI
UI
%
C O
4–101