EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 105
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EP1AGX20CF484C6N
Manufacturer Part Number
EP1AGX20CF484C6N
Description
IC ARRIA GX FPGA 20K 484FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX20CF484C6N
Number Of Logic Elements/cells
21580
Number Of Labs/clbs
1079
Total Ram Bits
1229184
Number Of I /o
230
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Arria™ GX
Number Of Logic Blocks/elements
21580
# I/os (max)
230
Process Technology
CMOS
Operating Supply Voltage (typ)
1.2V
Logic Cells
21580
Ram Bits
1229184
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
21580
Family Type
Arria GX
No. Of I/o's
230
Operating Frequency Max
622.08MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2395
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1AGX20CF484C6N
Manufacturer:
ALTERA
Quantity:
672
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Table 2–29. Supported TDO/TDI Voltage Combinations
High-Speed Differential I/O with DPA Support
© December 2009 Altera Corporation
Arria GX
Non-Arria GX
Notes to
(1) The TDO output buffer meets V
(2) The TDO output buffer meets V
(3) An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
(4) Input buffer must be 3.3-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
(6) Input buffer must be 1.8-V tolerant.
Device
Table
2–29:
Always V
Buffer Power
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
TDI Input
(3.3 V)
Arria GX devices contain dedicated circuitry for supporting differential standards at
speeds up to 840 Mbps. LVDS differential I/O standards are supported in the Arria
GX device. In addition, the LVPECL I/O standard is supported on input and output
clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high-speed I/O
interconnect standards and applications:
■
■
■
There are two dedicated high-speed PLLs (PLL1 and PLL2) in the EP1AGX20 and
EP1AGX35 devices and up to four dedicated high-speed PLLs (PLL1, PLL2, PLL7,
and PLL8) in the EP1AGX50, EP1AGX60, and EP1AGX90 devices to multiply
reference clocks and drive high-speed differential SERDES channels in I/O banks 1
and 2.
Table 2–30
in each of the Arria GX devices. In
transmitter or receiver provides the maximum number of channels that each fast PLL
can drive in its adjacent I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows
the maximum number of channels that each fast PLL can drive in both I/O banks
(I/O Bank 1 and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
Parallel RapidIO standard
C C P D
OH
OH
(MIN) = 2.4 V.
(MIN) = 2.0 V.
through
V
C C I O
v
v
v
v
v
(1),
(1),
(1),
= 3.3 V
(1)
(1)
(4)
(4)
(4)
Table 2–34
V
Arria GX TDO V
C C I O
v
v
v
v
v
list the number of channels that each fast PLL can clock
(2),
(2),
= 2.5 V
(2)
(2)
(2)
Table 2–30
(5)
(5)
C C I O
V
C C I O
Voltage Level in I/O Bank 4
v
v
v
v
through
v
= 1.8 V
(3)
(3)
(3)
(6)
Table 2–34
V
Level shifter
Level shifter
Level shifter
Level shifter
C C I O
required
required
required
required
Arria GX Device Handbook, Volume 1
v
= 1.5 V
the first row for each
V
Level shifter
Level shifter
Level shifter
Level shifter
C C I O
required
required
required
required
v
= 1.2 V
2–99