EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 200

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–78
Dedicated Clock Pin Timing
Arria GX Device Handbook, Volume 1
Table 4–77
devices.
Table 4–77. EP1AGX90 Column Pin Delay Adders for Regional Clock
Table 4–79
clock is driven by the global clock, regional clock, periphery clock, and a PLL.
Table 4–78
Table 4–78. Arria GX Clock Timing Parameters
EP1AGX20 Clock Timing Parameters
Table 4–79
devices.
Table 4–79
Table 4–79. EP1AGX20 Row Pins Global Clock Timing Parameters
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
t
t
t
t
tcin
tcout
tpllcin
tpllcout
CIN
COUT
PLLCIN
PLLCOUT
Parameter
Symbol
Parameter
lists column pin delay adders when using the regional clock in Arria GX
through
lists Arria GX clock timing parameters.
through
lists clock timing specifications.
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL inclk pad to I/O input register
Delay from PLL inclk pad to I/O output register
Table 4–98
Table 4–80
Industrial
–0.027
–0.022
1.394
1.399
Industrial
–1.697
–0.138
0.138
1.966
Fast Model
list clock pin timing for Arria GX devices when the
list the GCLK clock timing parameters for EP1AGX20
Fast Corner
Parameter
Commercial
–0.027
–0.022
1.394
1.399
Commercial
–1.697
–0.138
0.138
1.966
Chapter 4: DC and Switching Characteristics
–6 Speed Grade
© December 2009 Altera Corporation
3.161
3.155
0.091
0.085
–6 Speed Grade
–3.607
–0.353
0.354
5.188
Typical Design Performance
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns