EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 222

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–100
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
High-Speed I/O Specifications
Table 4–114. High-Speed Timing Specifications and Definitions (Part 1 of 2)
Arria GX Device Handbook, Volume 1
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
t
f
J
W
t
t
LVDS
High-Speed Timing Specifications
Maximum DCD (ps) for Row DDIO Output I/O Standard
C
H S C L K
R I S E
F A L L
Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path
Table 4–114
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
Maximum DCD (ps) for Column
DDIO Output I/O Standard
lists high-speed timing specifications definitions.
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
Arria GX Devices (PLL Output
Arria GX Devices (PLL Output
–6 Speed Grade
Feeding DDIO)
–6 Speed Grade
Feeding DDIO)
180
65
70
70
Definitions
160
110
100
155
100
155
180
95
75
70
65
80
70
70
70
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
Units
High-Speed I/O Specifications
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Units
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ps
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ps
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