EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 110

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–104
Fast PLL and Channel Layout
Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices
Note to
(1) For the number of channels each device supports, refer to
Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices
Note to
(1) For the number of channels each device supports, refer to
Arria GX Device Handbook, Volume 1
Figure
Figure
2–81:
2–82:
The receiver and transmitter channels are interleaved as such that each I/O bank on
the left side of the device has one receiver channel and one transmitter channel per
LAB row.
EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices.
fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.
4
2
4
2
2
2
2
2
Figure 2–81
4
4
4
4
PLL 1
PLL 2
PLL 7
PLL 1
PLL 2
PLL 8
Fast
Fast
Fast
Fast
Fast
Fast
LVDS
LVDS
LVDS
LVDS
Clock
Clock
Clock
Clock
shows the fast PLL and channel layout in the EP1AGX20C,
Table
Table 2–30
Clock
Clock
2–30.
Clock
Clock
DPA
DPA
DPA
DPA
through
Table
Quadrant
Quadrant
Quadrant
Quadrant
2–34.
(Note 1)
High-Speed Differential I/O with DPA Support
Quadrant
Quadrant
Quadrant
Quadrant
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Figure 2–82
shows the
(Note 1)