EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 5

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 1: Arria GX Device Family Overview
Features
Table 1–1. Arria GX Device Features (Part 2 of 2)
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
© December 2009 Altera Corporation
Source-
synchronous
transmit
channels
M512 RAM
blocks
(32 × 18 bits)
M4K RAM
blocks
(128 × 36
bits)
M-RAM
blocks
(4096 × 144
bits)
Total RAM
bits
Embedded
multipliers
(18 × 18)
DSP blocks
PLLs
Maximum
user I/O pins
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
EP1AGX35D
EP1AGX50D
Feature
Device
EP1AGX20C
1,229,184
230, 341
166
118
29
40
10
Transceiver
C
1
4
Channels
Arria GX devices are available in space-saving FBGA packages (refer to
Arria GX devices support vertical migration within the same package. With vertical
migration support, designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package across device
densities. For I/O pin migration across densities, the designer must cross-reference
the available I/O pins with the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
4
4
4
4
8
8
230
29
C
EP1AGX35C/D
1,348,416
Source-Synchronous Channels
Receive
31, 42
197
140
31
31
31
31
31
56
14
1
4
341
29
D
Transmit
29, 42
29
29
29
29
29
229
29
C
4
EP1AGX50C/D
2,475,072
313
242
104
26
2
350, 514
29, 42
4, 8
484-Pin FBGA
D
(23 mm)
230
230
229
229
—
—
Maximum User I/O Pin Count
229
29
C
EP1AGX60C/D/E
Arria GX Device Handbook, Volume 1
4
780-Pin FBGA
2,528,640
(29 mm)
326
252
128
350
341
341
350
29
32
—
—
—
D
2
Table
514
42
E
8
1–2). All
1152-Pin
(35 mm)
FBGA
514
—
—
—
—
—
1–3
EP1AGX90E
4,477,824
478
400
176
538
45
44
E
4
8