EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 17

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
Transceivers
Figure 2–12. External Termination and Biasing Circuit
© December 2009 Altera Corporation
The receiver has 100- on-chip differential termination (R
protocols, as shown in
if external terminations and biasing are provided. The receiver and transmitter
differential termination method can be set independently of each other.
Figure 2–11. Receiver Input Buffer
If a design uses external termination, the receiver must be externally terminated and
biased to 0.85 V or 1.2 V.
biasing circuit.
Programmable Equalizer
The Arria GX receivers provide a programmable receiver equalization feature to
compensate for the effects of channel attenuation for high-speed signaling. PCB traces
carrying these high-speed signals have low-pass filter characteristics. Impedance
mismatch boundaries can also cause signal degradation. Equalization in the receiver
diminishes the lossy attenuation effects of the PCB at high frequencies.
Termination
Resistance
50-W
Transmission
Line
Input
Pins
V
Receiver External Termination
and Biasing
DD
´ {R2/(R1 + R 2)} = 0.85/1.2 V
Receiver External Termination
Figure
R1/R2 = 1K
Termination
Figure 2–12
V
C1
100-Ω
and Biasing
DD
2–11. You can disable the receiver’s internal termination
shows an example of an external termination and
R2
R1
Programmable
Equalizer
Arria GX Device
RXIN
RXIP
Receiver
D
Arria GX Device Handbook, Volume 1
OCT) for different
Differential
Buffer
Input
2–11