EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 29

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
Transceivers
Reset and Powerdown
© December 2009 Altera Corporation
You can dynamically put the PCI Express (PIPE) mode transceiver in reverse parallel
loopback by controlling the tx_detectrxloopback port instantiated in the
MegaWizard Plug-In Manager. A high on the tx_detectrxloopback port in P0
power state puts the transceiver in reverse parallel loopback. A high on the
tx_detectrxloopback port in any other power state does not put the transceiver
in reverse parallel loopback.
As seen in
parallel loopback goes through the CRU, deserializer, word aligner, and the rate
matcher blocks. The parallel data at the output of the receiver rate matcher block is
looped back to the input of the transmitter serializer block. The serializer converts the
parallel data to serial data and feeds it to the transmitter output buffer that drives the
data out on the tx_dataout port. The data at the output of the rate matcher also
goes through the 8B/10B decoder, byte deserializer, and receiver phase compensation
FIFO before being fed to the PLD on the rx_dataout port.
Arria GX transceivers offer a power saving advantage with their ability to shut off
functions that are not needed.
The following three reset signals are available per transceiver channel and can be used
to individually reset the digital and analog portions within each channel:
■
■
■
The following two powerdown signals are available per transceiver block and can be
used to shut down an entire transceiver block that is not being used:
■
■
tx_digitalreset
rx_analogreset
rx_digitalreset
gxb_powerdown
gxb_enable
Figure
2–21, the serial data received on the rx_datain port in reverse
Arria GX Device Handbook, Volume 1
2–23