EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 68

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–62
Modes of Operation
Table 2–14. Multiplier Size and Configurations per DSP Block
DSP Block Interface
Arria GX Device Handbook, Volume 1
Multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
DSP Block Mode
The adder, subtractor, and accumulate functions of a DSP block have four modes of
operation:
■
■
■
■
Table 2–14
mode according to size. These modes allow the DSP blocks to implement numerous
applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR,
correlators, matrix multiplication, and many other functions. DSP blocks also support
mixed modes and mixed multiplier sizes in the same block. For example, half of one
DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode,
while the other half of the DSP block implements four 9 × 9-bit multipliers in simple
multiplier mode.
The Arria GX device DSP block input registers can generate a shift register that can
cascade down in the same DSP block column. Dedicated connections between DSP
blocks provide fast connections between shift register inputs to cascade shift register
chains. You can cascade registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit
FIR filters larger than four taps, with additional adder stages implemented in ALMs.
If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator
stages are implemented in ALMs. Each DSP block can route the shift register chain
out of the block to cascade multiple columns of DSP blocks.
The DSP block is divided into four block units that interface with four LAB rows on
the left and right. Each block unit can be considered one complete 18 × 18-bit
multiplier with 36 inputs and 36 outputs. A local interconnect region is associated
with each DSP block. Like an LAB, this interconnect region can be fed with 16 direct
link interconnects from the LAB to the left or right of the DSP block in the same row.
R4 and C4 routing resources can access the DSP block’s local interconnect region.
The outputs also work similarly to LAB outputs. Eighteen outputs from the DSP block
can drive to the left LAB through direct link interconnects and 18 can drive to the
right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4
routing interconnects. Outputs can drive right- or left-column routing.
Eight multipliers with eight
product outputs
Four two-multiplier adder (two
9 × 9 complex multiply)
Two four-multiplier adder
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
shows the different number of multipliers possible in each DSP block
9 × 9
—
Four multipliers with four
product outputs
Two 52-bit
multiply-accumulate blocks
Two two-multiplier adder (one
18 × 18 complex multiply)
One four-multiplier adder
18 × 18
© December 2009 Altera Corporation
One multiplier with one
product output
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
36 × 36
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—
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