EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 190

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–68
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 4 of 4)
Arria GX Device Handbook, Volume 1
3.3-V PCI
3.3-V PCI-X
LVDS
I/O Standard
Strength
Drive
—
—
—
Table 4–70
should be added to the GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Table 4–70
devices.
Table 4–70. EP1AGX60 Row Pin Delay Adders for Regional Clock
Table 4–71
devices.
Table 4–71. EP1AGX60 Column Pin Delay Adders for Regional Clock
EP1AGX90 I/O Timing Parameters
Table 4–72
EP1AGX90 devices for I/O standards which support general purpose I/O pins.
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
GCLK PLL
GCLK PLL
GCLK PLL
Parameter
Parameter
GCLK
GCLK
GCLK
Clock
through
describes row pin delay adders when using the regional clock in Arria GX
lists column pin delay adders when using the regional clock in Arria GX
through
Table 4–71
Table 4–75
Parameter
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
Industrial
Industrial
list EP1AGX60 regional clock (RCLK) adder values that
–0.003
–0.138
list the maximum I/O timing parameters for
–1.066
–0.153
0.138
0.003
0.153
1.721
Industrial
2.882
1.312
2.882
1.312
3.746
2.185
Fast Corner
Fast Corner
Fast Corner
Commercial
Commercial
Commercial
–0.003
–0.138
–1.066
–0.153
0.138
0.003
0.153
1.721
2.882
1.312
2.882
1.312
3.746
2.185
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
–6 Speed Grade
–6 Speed Grade
–6 Speed
Grade
6.213
2.778
6.213
2.778
7.396
3.973
–0.006
–0.311
–2.338
–0.343
Typical Design Performance
0.311
0.006
0.344
4.486
Units
ns
ns
ns
ns
ns
ns
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns