EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 108

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–102
Table 2–34. EP1AGX90 Device Differential Channels
Dedicated Circuitry with DPA Support
Figure 2–79. Arria GX Transmitter Channel
Arria GX Device Handbook, Volume 1
1,152-pin FineLine
BGA
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Package
Table
2–34:
refclk
Arria GX devices support source-synchronous interfacing with LVDS signaling at up
to 840 Mbps. Arria GX devices can transmit or receive serial channels along with a
low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1 through 32.
The SERDES factor J determines the parallel data width to deserialize from receivers
or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10
and does not have to equal the PLL clock-multiplication W value. A design using the
dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the
Arria GX device bypasses the SERDES block. For a J factor of 2, the Arria GX device
bypasses the SERDES block, and the DDR input and output registers are used in the
IOE.
Each Arria GX receiver channel features a DPA block for phase detection and
selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the
dynamic phase aligner without affecting the basic source-synchronous operation of
the channel. In addition, you can dynamically switch between using the DPA block or
bypassing the block via a control signal from the logic array.
Transmitter
Receiver
Transmitter/Receiver
Figure 2–79
Fast
PLL
Data from R4, R24, C4, or
direct link interconnect
Interconnect
Local
shows the block diagram of the Arria GX transmitter channel.
diffioclk
load_en
10
Total Channels
(Note 1)
10
45
47
PLL1
23
22
23
24
Center Fast PLLs
Dedicated
Transmitter
Interface
+
–
High-Speed Differential I/O with DPA Support
Regional or
global clock
Up to 840 Mbps
© December 2009 Altera Corporation
PLL2
22
23
24
23
Chapter 2: Arria GX Architecture
Corner Fast
PLL7
PLLs
23
—
23
—