EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 43

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
© December 2009 Altera Corporation
Figure
2–33:
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(1)
Figure 2–32. Six-Input Function in Normal Mode
Notes to
(1) If datae1 and dataf1 are used as inputs to the six-input function, datae0 and dataf0 are available for register
(2) The dataf1 input is available for register packing only if the six-input function is un-registered.
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input functions. The
set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs.
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing. Functions that fit into the
template shown in
appear in designs as “if-else” statements in Verilog HDL or VHDL code.
packing.
Figure
This input is available
for register packing.
Figure 2–33
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(2)
2–32:
5-Input
5-Input
LUT
LUT
These inputs are available for register packing.
Figure 2–33
shows the template of supported seven-input functions utilizing
combout0
6-Input
LUT
occur naturally in designs. These functions often
Note (1), (2)
D
reg0
Q
D
D
reg0
reg1
Q
Q
To general or
To general or
local routing
local routing
Arria GX Device Handbook, Volume 1
To general or
local routing
To general or
local routing
To general or
local routing
2–37