EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 25

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
Transceivers
© December 2009 Altera Corporation
8B/10B Decoder
The 8B/10B decoder is used in all supported functional modes. The 8B/10B decoder
takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control
identifier, thereby restoring the original transmitted data at the receiver. The 8B/10B
decoder indicates whether the received 10-bit character is a data or control code
through the rx_ctrldetect port. If the received 10-bit code group is a control
character (Kx.y), the rx_ctrldetect signal is driven high and if it is a data
character (Dx.y), the rx_ctrldetect signal is driven low.
Figure 2–17
indicator.
Figure 2–17. 10-Bit to 8-Bit Conversion
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B
decoder block asserts an error flag on the rx_errdetect port. If the received 10-bit
code is detected with incorrect running disparity, the 8B/10B decoder block asserts an
error flag on the rx_disperr and rx_errdetect ports. The error flag signals
(rx_errdetect and rx_disperr) have the same data path delay from the 8B/10B
decoder to the PLD-transceiver interface as the bad code group.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express (PIPE), and XAUI
modes. In GIGE mode, the receiver state machine replaces invalid code groups with
K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group
to the XAUI XGMII code group.
shows a 10-bit code group decoded to an 8-bit data and a 1-bit control
MSB Received Last
ctrl
9
j
h
8
H
7
g
7
G
6
6
8B/10B Conversion
f
5
F
5
i
E
4
e
4
3
D
d
3
2
C
c
2
B
1
LSB Received First
b
1
0
A
Arria GX Device Handbook, Volume 1
Parallel Data
a
0
2–19