EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 226
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EP1AGX20CF484C6N
Manufacturer Part Number
EP1AGX20CF484C6N
Description
IC ARRIA GX FPGA 20K 484FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX20CF484C6N
Number Of Logic Elements/cells
21580
Number Of Labs/clbs
1079
Total Ram Bits
1229184
Number Of I /o
230
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Arria™ GX
Number Of Logic Blocks/elements
21580
# I/os (max)
230
Process Technology
CMOS
Operating Supply Voltage (typ)
1.2V
Logic Cells
21580
Ram Bits
1229184
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
21580
Family Type
Arria GX
No. Of I/o's
230
Operating Frequency Max
622.08MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2395
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1AGX20CF484C6N
Manufacturer:
ALTERA
Quantity:
672
4–104
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)
Table 4–117. Fast PLL Specifications (Part 1 of 2)
Arria GX Device Handbook, Volume 1
t
Notes to
(1) This is limited by the I/O f
(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.
f
f
f
t
f
f
f
t
f
t
t
t
RECONFIGWAIT
IN
INPFD
INDUTY
INJITTER
VCO
OUT
OUT_EXT
CONFIGPLL
CLBW
LOCK
PLL_PSERR
ARESET
Name
Table
Name
4–116:
The time required for the wait after the
reconfiguration is done and the areset is
applied.
Input clock frequency
Input frequency to the
PFD
Input clock duty cycle
Input clock jitter
tolerance in terms of
period jitter.
Bandwidth
Input clock jitter
tolerance in terms of
period jitter.
Bandwidth 0.2 MHz
Upper VCO frequency
range
Lower VCO frequency
range
PLL output frequency
to
PLL output frequency
to LVDS or DPA clock
PLL clock output
frequency to regular
I/O
Time required to
reconfigure scan
chains for fast PLLs
PLL closed-loop
bandwidth
Time required for the
PLL to lock from the
time it is enabled or
the end of the device
configuration
Accuracy of PLL phase
shift
Minimum pulse width
on
MAX
GCLK
areset
.
Description
or
RCLK
signal.
2 MHz
Description
4.6875
4.6875
16.08
16.08
1.16
Min
300
150
150
40
—
—
—
—
—
10
75/f
0.03
Typ
0.5
1.0
—
—
—
—
—
—
—
—
SCANCLK
—
—
5
Min
—
Chapter 4: DC and Switching Characteristics
Max
640
500
840
420
550
840
±30
Typ
—
(1)
60
—
—
—
28
—
1
© December 2009 Altera Corporation
Max
2
PLL Timing Specifications
ns (p-p)
ns (p-p)
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ns
ps
ns
%
Units
us