EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 76

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–70
Figure 2–58. Global Clock Control Blocks
Notes to
(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode.
(2) These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object File [.pof]) and cannot be
Figure 2–59. Regional Clock Control Blocks
Notes to
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode
(2) Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Arria GX Device Handbook, Volume 1
dynamically controlled during user mode operation.
operation.
Figure
Figure
2–58:
2–59:
Clock Control Block
Each GCLK, RCLK, and PLL external clock output has its own clock control block.
The control block has two functions:
■
■
Figure 2–58
regional clock, and PLL external clock output, respectively.
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
CLKSELECT[1..0]
(1)
This multiplexer supports
User-Controllable
Dynamic Switching
through
PLL Counter
PLL Counter
Outputs
Outputs
Figure 2–60
2
2
2
CLKp
CLKp
Pins
Pin
Enable/
Disable
RCLK
2
CLKn
Pin
show the clock control block for the global clock,
Enable/
Disable
GCLK
CLKn
Pin
(2)
Internal
Logic
Static Clock Select (1)
Internal
Logic
Internal
Logic
Internal
Static Clock Select
Logic
(2)
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks