EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 209

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–101. Arria GX IOE Programmable Delay on Column Pins
Maximum Input and Output Clock Toggle Rate
© December 2009 Altera Corporation
Input delay
from pin to
internal cells
Input delay
from pin to
input register
Delay from
output
register to
output pin
Output
enable pin
delay
Parameter
Pad to I/O input register
I/O output register to
Pad to I/O dataout to
Paths Affected
Table 4–101
Maximum clock toggle rate is defined as the maximum frequency achievable for a
clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated
clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit rate. If the
maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit
rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same
I/O pin.
Table
capacitive loading. Use the Quartus II software to obtain output toggle rates at loads
different from the default capacitive loading.
Table 4–102
I/O pins.
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
txz/tzx
core
pad
I/O Standards
4–105,
shows the maximum input clock toggle rates for Arria GX device column
lists IOE programmable delays.
Table
Available
Settings
4–106, and
64
8
2
2
–6 Speed Grade
Offset
Min
Table 4–107
0
0
0
0
Industrial
420
420
420
420
420
467
467
467
Offset
1.781
2.053
0.332
0.32
Max
Fast Model
provide output toggle rates at the default
Offset
Min
Commercial
0
0
0
0
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Offset
1.781
2.053
0.332
Max
0.32
Arria GX Device Handbook, Volume 1
–6 Speed Grade
Offset
Min
0
0
0
0
Offset
4.132
4.697
0.717
0.693
Max
Units
ns
ns
ns
ns
4–87