TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 6

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY TXC-06312B-MB, Ed. 2
June 2005
PHAST-12N Device
DATA SHEET
TXC-06312B
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Supported SDH/SONET Mapping .................................................................................................................. 13
PHAST-12N TXC-06312B Block Diagram ...................................................................................................... 17
PHAST-12N Functional Model........................................................................................................................ 18
PHAST-12N TXC-06312B 376-Lead Plastic Ball Grid Array Package Lead Diagram.................................... 21
DROP Bus Timing .......................................................................................................................................... 54
Add Bus Timing (ADD Slave Mode: Timing Signals Are Inputs)..................................................................... 55
ADD Bus Timing (ADD Master Mode: Timing Signals Are Outputs)............................................................... 56
RX TOH Byte Interface ................................................................................................................................... 57
TX TOH Byte Interface ................................................................................................................................... 58
RX High Order POH Byte Interface ................................................................................................................ 59
TX High Order POH Byte Interface................................................................................................................. 60
RX Line Ring Port Interface ............................................................................................................................ 61
TX Line Ring Port Interface ............................................................................................................................ 62
RX Path Alarm Indication Port Interface ......................................................................................................... 63
TX Path Alarm Indication Port Interface ......................................................................................................... 64
Relationship Between the External Frame Reference Pulse (REFTXFS)
and the Generated Internal Frame Reference Pulse (REFSYSFS) ............................................................... 65
Relationship Between REFSYSFS, Add and Drop Telecom Bus Timing Signals........................................... 67
Microprocessor Interface: Generic Intel Mode Write Cycle ............................................................................ 68
Microprocessor Interface: Generic Intel Mode Read Cycle ............................................................................ 70
Microprocessor Interface: Generic Motorola Mode Write Cycle ..................................................................... 72
Microprocessor Interface: Generic Motorola Mode Read Cycle ..................................................................... 74
Microprocessor Interface: Motorola MPC860 Mode Write Cycle.................................................................... 76
Microprocessor Interface: Motorola MPC860 Mode Read Cycle.................................................................... 78
Microprocessor Interface: Motorola MPC8260 Local Bus Mode Write Cycle ................................................. 80
Microprocessor Interface: Motorola MPC8260 Local Bus Mode Read Cycle................................................. 82
Boundary Scan Timing ................................................................................................................................... 84
Clock Recovery/Clock Synthesis .................................................................................................................... 88
STM-1/OC-3, 1:3 APS with one PHAST-12N ............................................................................................... 103
APS Port Architecture................................................................................................................................... 104
STM-4/OC-12, 1+1 APS ............................................................................................................................... 105
STM-4/OC-12, 1:1 APS ................................................................................................................................ 106
STM-1/OC-3, 1+1 APS Idle State................................................................................................................. 107
STM-1/OC-3, 1+1 APS Switch State ............................................................................................................ 108
STM-1/OC-3, 1:1 APS Idle State .................................................................................................................. 108
STM-1/OC-3, 1:1 APS Switch State ............................................................................................................. 109
STM-1/OC-3, 1:7 APS Idle State .................................................................................................................. 110
STM-1/OC-3, 1:7 APS Switch State ............................................................................................................. 111
STM-1/OC-3, 1:7 APS Switch State ............................................................................................................. 111
Frame Reference Pulse Generation ............................................................................................................. 113
Retimer FIFO Filling Levels .......................................................................................................................... 114
Internal Line Alarm Indication (Ring) Port Interface...................................................................................... 124
External Line Alarm Indication (Ring) Port Interface..................................................................................... 125
Internal High Order Alarm Indication (Ring) Port Interface ........................................................................... 129
External High Order Alarm Indication (Ring) Port Interface.......................................................................... 130
HINT ............................................................................................................................................................. 140
High Order Point Tracker Retimer Interrupt Tree.......................................................................................... 140
POH Monitor Interrupt Tree .......................................................................................................................... 141
TOH Monitor Interrupt Tree........................................................................................................................... 142
APS Interrupt Tree (part 1) ........................................................................................................................... 143
APS Interrupt Tree (part 2) ........................................................................................................................... 144
General Interrupt Tree (part 1)...................................................................................................................... 145
General Interrupt Tree (part 2)...................................................................................................................... 146
General Interrupt Tree (part 3)...................................................................................................................... 147
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