TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 121

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 2 1 o f 2 02
A9
11.7 TOH PORT INTERFACE
11.7.1 Transmit TOH Port Interface
(range 0 to 8)
Row number
A8
a-1
The transmit TOH port interface allows insertion of the RSOH and MSOH bytes into the TOH.
All received TOH bytes are output on the receive TOH port interface.
Each interface consists of clock, data, data enable, address and address enable lines.
The address is a 10-bit word according to the (a, b, c) format specified by ITU-T G.707/Y.1322
clause 9.2.1 and Figure 9-1:
This port interface allows insertion of the RSOH and MSOH bytes into the TOH. The TOH
port interface is used to request any of the TOH bytes for either one STM-4 or four STM-1
frames from the outside world. Note the BIP bytes (B1, B2) have a special meaning, these
can be used as an error mask on the calculated BIP.
The Transmit TOH Port consists of following leads:
The transmit TOH Port protocol is as follows (see
Note: Configuration of the Transmit TOH Port interface is done in the memory map of the
TOH Generator (see
the TOH bytes internal memory by setting the most significant bit of the corresponding
memory entry to ‘1’.
• Output Transmit TOH Port Clock TOHTXCLK
• Output Transmit TOH Port Address Latch Enable TOHTXALE
• Output Transmit TOH Port Address TOHTXADDR
• Output Transmit TOH Port Data Latch Enable TOHTXDLE
• Input Transmit TOH Port Data TOHTXDATA
1. The 10-bit address for the requested byte is output on TOHTXADDR, most significant
2. A one cycle gap is left open.
3. The Data Latch Enable TOHTXDLE is asserted and the 8-bit data word is sampled on
A7
- High Order Pointer Tracking, Retiming and Pointer Generation -
bit first. During this time the Address Latch Enable TOHTXALE is asserted.
the input TOHTXDATA, most significant bit first.
A6
A5
Table
(Multi-)Column number
A4
29). Selection of the TOH Port as source for a TOH byte is done in
(range 0 to 8)
b-1
A3
A2
Figure
STM-1/OC-3 Line
Interleave Depth
(range 0 to 3)
Multi-Column
(range 0 to 3)
A1
9):
c-1
PRELIMINARY TXC-06312B-MB, Ed. 2
A0
PHAST-12N Device
Line Interface Mode
STM-4/OC-12 Mode
STM-1/OC-3 Mode
DATA SHEET
TXC-06312B
June 2005