TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 155

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 5 5 o f 2 02
Offset
Offset
0x000C 11 - 0
0x000A 15 - 0
0x000E 15 - 0
0x0000 7 - 0
9 - 8
10
Bits
Bits
GeneralInterrupts
APS_Interrupts
GeneralInterrupts_Mask
ResetCounters
LatchForIntCtrl
Reserved
Name
Name
Table 8: Interrupt Configuration
- Memory Maps and Bit Descriptions -
Table 7: Interrupt
Init
0xFFFF rw
0x0 All performance counters are reset when the value 0x91 is written to this
0x3 0x0 = INT_LEVEL
0x0 Reserved.
Init
0x0 ro
0x0 ro
register. Reset is active as long this register contains the value 0x91.
0x1 = INT_RISING_EDGE
0x2 = INT_FALLING_EDGE
0x3 = INT_BOTH_EDGES
Field to control on which edges the unlatched defects are latched for
interrupts.
Access
(T_INTERRUPT)
(T_InterruptCtrl_Config)
General Interrupts Register:
APS Interrupts Register:
General Interrupts Mask.
See GeneralInterrupts register for details.
• bit 0: Global Control Interrupt
• bit 1: Terminal Retimer
• bit 2: Add Telecombus
• bit 3: Reserved
• bit 4: Reserved
• bit 5: Reserved
• bit 6: POH Ring Port
• bit 7: Terminal POH Monitor
• bit 8: Line Pointer Tracker/Retimer
• bit 9: TOH Ring Port
• bit 10: Receive TOH/DCC Port
• bit 11: TOH Monitor Line 1
• bit 12: TOH Monitor Line 2
• bit 13: TOH Monitor Line 3
• bit 14: TOH Monitor Line 4
• bit 15: Mixed Signal
• bit 0: APS Pointer Tracker/Retimer
• bit 1: Receive APS
• bit 2: APS POH Monitor
• bit 3: Line POH Monitor
• bit 4: Receive APS Line 1
• bit 5: Receive APS Line 2
• bit 6: Receive APS Line 3
• bit 7: Receive APS Line 4
• bit 8: TOH Monitor APS Line 1
• bit 9: TOH Monitor APS Line 2
• bit 10: TOH Monitor APS Line 3
• bit 11: TOH Monitor APS Line 4
Description
PRELIMINARY TXC-06312B-MB, Ed. 2
Description
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005