TXC-06885BIOG Transwitch Corporation, TXC-06885BIOG Datasheet

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TXC-06885BIOG

Manufacturer Part Number
TXC-06885BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-06885BIOG

Operating Supply Voltage (typ)
1.8/3.3V
Operating Temperature Classification
Industrial
Package Type
BGA
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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Part Number:
TXC-06885BIOG
Manufacturer:
TRANSWITCH
Quantity:
10
Part Number:
TXC-06885BIOG
Manufacturer:
TRANSWI
Quantity:
17
PRELIMINARY
APPLICATIONS
FEATURES
TranSwitch Corporation
Tel: 203-929-8810
4 Configurable Media Access Controllers (MACs)
Each MAC is configurable as 8 Fast Ethernet ports (10/100 Mbit/s), 2 Fast Ethernet
ports with extended buffers or 1 Gigabit Ethernet port (10/100/1000 Mbit/s)
SPI-3 interface configurable in Link or PHY layer mode, operating at 125 MHz
Support for Jumbo frames (9600 Bytes) and Super Jumbo frames (12000 Bytes)
Full and Half Duplex (CSMA/CD) operation (Half Duplex only supported for Fast
Ethernet)
Programmable SPI-3 burst size from 64 to 1024 bytes
Frame integrity verification (FCS and Frame length checks) and generation
Packet statistics and Performance monitoring support for RMON per port
PAUSE frame flow control for Full Duplex mode
“Raise Carrier” flow control for Half Duplex mode
Programmable high and low FIFO watermarks for flow control trigger
Automatic PAUSE frame generation and termination
Filtering of PAUSE frames in Ethernet Ingress or Egress
Port aggregation from Ethernet to SPI-3, using routing tag encapsulation
8/16 bit Microprocessor interface, selectable between Intel or Motorola
JTAG Boundary Scan (IEEE 1149.1 Standard)
580-lead Plastic Ball Grid Array (PBGA) package, 27 mm x 27 mm
Metro Edge Routers and Switches
Ethernet over SONET/SDH Multi-Service Provisioning Platforms (MSPPs)
IP DSLAMs
3G Wireless Base Stations
3G Radio Network Controllers (RNCs)
Multi-Service Access Platforms (MSAPs)
Network Side
(SMII/MII/GMII)
4 10/100/1000
32 10/100
3 Enterprise Drive
Ethernet
Fax: 203-926-9453
Ethernet Controller
Shelton, Connecticut 06484
8/16 bit @ 33/66 MHz
Envoy-CE4
TXC-06885
MMII
Host Interface
SPI-3 to
www.transwitch.com
Envoy-CE4 Device
JTAG
SPI-3 to Ethernet Controller
TM
Switch Side
TXC-06885-MB, Ed. 6A
USA
SPI-3
8/16/32 bit
@ 104/125 MHz
DATA SHEET
February 2005
TXC-06885

Related parts for TXC-06885BIOG

TXC-06885BIOG Summary of contents

Page 1

... Ethernet SPI-3 to (SMII/MII/GMII) Ethernet Controller 32 10/100 4 10/100/1000 TXC-06885 MMII • 3 Enterprise Drive • Shelton, Connecticut 06484 • Fax: 203-926-9453 • www.transwitch.com TM SPI-3 to Ethernet Controller TXC-06885 DATA SHEET TXC-06885-MB, Ed. 6A February 2005 Switch Side SPI-3 8/16/32 bit @ 104/125 MHz JTAG • USA ...

Page 2

... Applications Engineering for current information on this product. U.S. Patents No. 4,967,405; 5,040,170; 5,142,529; 5,265,096; 5,331,641; 5,724,362; 6,577,651B1 U.S. and/or foreign patents issued or pending Copyright 2005 TranSwitch Corporation Envoy is a trademark of TranSwitch Corporation TranSwitch, TXC and PHAST are registered trademarks of TranSwitch Corporation IMPORTANT NOTICE - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 3

... Receive MAC Data Flow....................................................................................................... 65 6.1.2 Receive MAC Checks ........................................................................................................... 65 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.2.5 6.1.3 Receive MAC Statistics ........................................................................................................ 66 6.1.3.1 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 T ABLE OF PHY Mode ................................................................................................................... 17 Link Mode .................................................................................................................... 18 Boundary Scan Operation ........................................................................................... 20 Boundary Scan Reset.................................................................................................. 20 Boundary Scan Schematic .......................................................................................... 21 Boundary Scan Chain.................................................................................................. 21 FCS Check: ................................................................................................................. 65 Frame Length Check: ...

Page 4

... Pad Short Ethernet Frames Option:............................................................................ 73 Frame Length Check:.................................................................................................. 73 Maximum Frame Size Check: ..................................................................................... 73 Back to Back Interframe Gap Option: ......................................................................... 73 Source Address Replace Option:................................................................................ 73 PAUSE Frame Filter Option: ....................................................................................... 73 Preamble Length Option: ............................................................................................ 73 Counters:..................................................................................................................... 73 Automatic PAUSE Frame Generation......................................................................... 77 Host Initiated PAUSE Frame Generation.................................................................... 78 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 5

... SMII Sync In/Out Timing ............................................................................................................. 50 12. SMII Transmit Interface Timing ................................................................................................... 51 13. SMII Receive Interface Timing .................................................................................................... 51 14. GMII Transmit Interface Timing Using GmTXCLKI ..................................................................... 52 15. GMII/MII Receive Interface Timing Using GmRXCLK ................................................................. 53 16. MII Transmit Interface Timing Using GmMTXCLK ...................................................................... 54 17. Management MII Interface Timing............................................................................................... 55 18. ...

Page 6

... Modified Description for Bit Range 7-0 of Address 93 Modified Description for Bit Range 7-0 of Address IST OF ATA HEET Summary of the Change “2010” C HANGES and “2014”. “2008” and “200C”. “2010” and “2014”. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 7

... Fast Ethernet and Gigabit Ethernet PHY/SerDes devices via the SMII and GMII. The Envoy-CE4 incorporates on-chip buffering to promote high performance without congestion or loss of data and provides backpressure support on both the Ethernet and SPI-3 interfaces. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 Envoy-CE4 Device DATA SHEET TXC-06885 1 ...

Page 8

... Common Connector having all the GMII & SMII Signals plus configuration pins to configure the Ethernet interface of the Envoy-CE4. Ethernet over SONET/SDH Line card GFP/VCAT FRAMER Envoy-CE4 FE = Fast Ethernet (10/100 Mbit/ Gigabit Ethernet (10/100/1000 Mbit/s) PRELIMINARY TXC-06885-MB, Ed. 6A PACKET SWITCH TDM SWITCH February 2005 ...

Page 9

... RMON STATUS, CONFIGURATION and MICROPROCESSOR INTERFACE Note: Each MAC is configurable as 8 Fast Ethernet Ports (10/100 Mbit/s), 2 Fast Ethernet Ports with Extended Buffers Gigabit Ethernet Port (10/100/1000 Mbit/s) Figure 2. Functional Block Diagram of the Envoy-CE4 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - 2.0 F ...

Page 10

... Programmable maximum frame length • Minimum frame size = 64 bytes • Maximum frame size = 12 KBytes • Support for VLAN tagged frame transmission • Programmable High and Low FIFO watermarks for space and frame/chunk availabil- ity generation Functional Description - - OR OR PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 11

... Both the transmit and receive clocks are inputs to the Envoy-CE4 • Four Status signals (Rx Data Valid, Tx Enable, Carrier sense, and Collision detect) Note: The GMII signal pins are muxed with the SMII signal pins. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - ...

Page 12

... When CMAC D is configured in Extended SMII mode (CFGCMACD = 10), ports 24 and 28 will be in extended SMII mode and ports 25, 26, 27, 29, 30, and 31 are inactive. When CMAC D is configured in SMII mode (CFGCMACD = 11), ports will be in SMII mode Functional Description - - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 13

... Note: Series termination resistor values are dependent on the selection of the Ethernet PHY. Please consult the specification of the Ethernet PHY for series termination resistor values Figure 3. GMII (1000 Mbit/s) Only Interface Connection PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - SMII Reference Clock is needed for ...

Page 14

... G(A,B,C,D)RXDV G(A,B,C,D)RXER G(A,B,C,D)COL G(A,B,C,D)CRS G(A,B,C,D)MTXCLK SMII Reference Clock is needed for Ethernet Statistics Clocking 125 MHz Reference Clock TxData[0-3] TxData[4-7] GMII 125 MHz TxClk TxEnable TxError RxClk (2.5/25/125 MHz) RxData[0-3] RxData[4-7] RxDataValid RxError Collision (Half Duplex Only) Carrier (CRS) (Half Duplex Only) MII 2 ...

Page 15

... When Scan mode and Auto PHY address increment are enabled, the range of addresses scanned will be between “PHY Address” (Register 0x0048 Bits 8-12) and PHY number 31. 2. Envoy’s Management Media Independent Interface (MMII Master mode. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - ...

Page 16

... SPI-3 address. Individual SPI-3 port addresses are calculated by adding the (base address x 32) to the logical Ethernet port number. For example, the SPI-3 address of port 19 with a base address of 3 will give a SPI-3 port address of (19 + (3x32)) =115 Functional Description - - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 17

... Packet data may be transferred across the Receive Interface in chunks, programmable from 8 to 2040 bytes byte increments. In the Receive direction (SPI-3 output), the time between consecutive transfers (pause) is programmable cycles. Figure 7. Envoy-CE4 in PHY Layer Mode PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - TFCLK TENB ...

Page 18

... OSPIMOD[1:0 ] STPA OSPISTPA PTPA OSPIPTPA TADR[7:0] OSPITADR[7:0] RFCLK ISPICLK RENB ISPIRENB RDAT[31:0] ISPID[31:0] RPRTY ISPIPRTY RVAL ISPIRVAL RSOP ISPISOP REOP ISPIEOP RERR ISPIERR RSX ISPIRSX RMOD[1:0] ISPIMOD[1:0] ISPITENB ISPISTPA ISPIPTPA ISPITADR[7:0] ISPITSX OSPIRENB OSPIRVAL OSPIRSX Envoy-CE4 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 19

... Test Mode Reset (TRST). The output signal is Test Data Output (TDO). In addition to the TAP, a pin is provided (DEVHIZ) to place the output buffers in a high impedance state for systems that do not support the IEEE 1149.1 standard. Boundary scan signal timing is shown in 20. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - Intel Mode Description ...

Page 20

... V Input, Output and Input/Output Parameters section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor Functional Description - - Figure 9. requirements listed in the IL PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 21

... Boundary Scan Schematic 2.1.9.4 Boundary Scan Chain A Boundary Scan Description Language (BSDL) source file for the Envoy-CE4 is available via the Products page of the TranSwitch Internet World Wide Web site at www.transwitch.com. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Functional Description - Boundary Scan Register ...

Page 22

... This is the bottom view and the leads are solder balls. See 2. Power supply leads are shown as solid black circles and ground leads are shown as cross- hatched circles. Figure 10. Envoy-CE4 Lead Diagram Technical Characteristics - - 3.0 T ECHNICAL BOTTOM VIEW HARACTERISTICS Figure 25 for package information. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 23

... Vt=500mV~600mV). This prevents from turning on the parasitic diode between power rails, avoiding latch up. The external diode will be turned off when V its normal voltage. *Note Input Output Power Tristate PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O/P * ...

Page 24

... NC lead, but must be left floating. Connection of NC leads may impair performance or cause damage to the device. Some NC leads may be assigned functions in future upgrades of the device. Backwards compatibility of the upgraded device in existing applications may rely upon these leads having been left floating. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 25

... TCK D22 RESET B16 TSTMODE A17 SCAN C16 TEST1 B17 DEVHIZ C17 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O Type O(T) CMOS Test Data Output: Boundary scan output for data 4 mA and test instructions from internal test registers. I LVTTLpu Test Mode Reset microsecond (minimum) low on this lead resets the boundary scan ...

Page 26

... Note: Device asserts this high before tri-stating to improve acknowledge timing. I LVTTL Microprocessor Address Bus: 15-bit address bus used by the Host Processor for accessing the Envoy- CE4 for a read/write cycle. UPA14 is the Most Significant Bit (MSB). Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 27

... B15 COMMON SMII INTERFACES PINS FOR ALL SMII PORTS (Ports 0 to 31) including extended SMII ports Symbol Lead No. SSYNCIN D25 SSYNCDIR E24 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O/P* Type I/O LVTTL/ Microprocessor Data Bus: Bi-directional 16-bit data CMOS bus used for transferring data between the Envoy CE4 and the Host Processor ...

Page 28

... Transmit Data Port 6: SMII port 6 data out signal 12mA I LVTTL Receive Data Port 6: SMII port 6 data in signal. O CMOS Transmit Data Port 7: SMII port 7 data out signal. 12mA I LVTTL Receive Data Port 7: SMII port 7 data in signal. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 29

... TX5B T5 RX5B V1 TX6B U4 RX6B V2 TX7B W1 RX7B V3 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O/P* Type I LVTTL SMII Reference Clock for Configurable MAC B: 125 MHz Clock. Must be active to support the Ethernet statistics registers of CMAC B - even when the CMAC is configured for GMII Mode. O ...

Page 30

... Transmit Data Port 22: SMII port 22 data out signal. 12mA I LVTTL Receive Data Port 22: SMII port 22 data in signal. O CMOS Transmit Data Port 23: SMII port 23 data out signal. 12mA I LVTTL Receive Data Port 23: SMII port 23 data in signal. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 31

... RX5D V24 TX6D U22 RX6D W25 TX7D V23 RX7D Y26 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O/P* Type I LVTTL SMII Reference Clock for Configurable MAC D: 125 MHz Clock. Must be active to support the Ethernet statistics registers of CMAC D - even when the CMAC is configured for GMII Mode. ...

Page 32

... Transmit Data Port 2A: Bit 2 of 8-bit GMII A Transmit 12mA Interface in GMII mode or Bit 2 of 4-bit MII A Transmit interface. I LVTTL Receive Data Port 2A: Bit 2 of 8-bit GMII A Receive Interface in GMII mode or Bit 2 of 4-bit MII A Receive interface. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 33

... GMII A (MII Mode) Carrier Sense: This active high input signal is the carrier sense lead used in MII mode for the GMII A interface. I LVTTL GMII A (MII Mode) TXCLK: This is the TXCLK signal used in MII mode for the GMII A interface. Envoy-CE4 Device DATA SHEET TXC-06885 ...

Page 34

... Transmit Data Port 2B: Bit 2 of 8-bit GMII B Transmit 12mA Interface in GMII mode or Bit 2 of 4-bit MII B Transmit interface. I LVTTL Receive Data Port 2B: Bit 2 of 8-bit GMII B Receive Interface in GMII mode or Bit 2 of 4-bit MII B Receive interface. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 35

... GMII B (MII Mode) Carrier Sense: This active high input signal is the carrier sense lead used in MII mode for the GMII B interface. I LVTTL GMII B (MII Mode) TXCLK: This is the TXCLK signal used in MII mode for the GMII B interface. Envoy-CE4 Device DATA SHEET TXC-06885 ...

Page 36

... Transmit Data Port 2C: Bit 2 of 8-bit GMII C 12mA Transmit Interface in GMII mode or Bit 2 of 4-bit MII C Transmit interface. I LVTTL Receive Data Port 2C: Bit 2 of 8-bit GMII C Receive Interface in GMII mode or Bit 2 of 4-bit MII C Receive interface. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 37

... GMII C (MII Mode) Carrier Sense: This active high input signal is the carrier sense pin used in MII mode for the GMII C interface. I LVTTL GMII C (MII Mode) TXCLK: This is the TXCLK signal used in MII mode for the GMII C interface. Envoy-CE4 Device DATA SHEET TXC-06885 ...

Page 38

... Transmit Data Port 2D: Bit 2 of 8-bit GMII D 12mA Transmit Interface in GMII mode or Bit 2 of 4-bit MII D Transmit interface. I LVTTL Receive Data Port 2D: Bit 2 of 8-bit GMII D Receive Interface in GMII mode or Bit 2 of 4-bit MII D Receive interface. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 39

... LVTTL GMII D (MII Mode) Carrier Sense: This active high input signal is the carrier sense pin used in MII mode for the GMII D interface. I LVTTL GMII D (MII Mode) TXCLK: This is the TXCLK signal used in MII mode for the GMII D interface. I/O/P* Type O CMOS ...

Page 40

... SPI-3 Mode: ISPID(31-0); ISPID31 is MSB. I LVTTL SPI-3 Input Bus Parity: This input signal indicates the parity calculated over the ISPID(31-0) bus, when start of transfer or read (Link layer mode)/write (PHY layer mode) enable signals are asserted. Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 41

... ISPITADR2 AB11 ISPITADR1 AF9 ISPITADR0 AC10 ISPISTPA AC12 ISPIPTPA AF11 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O/P* Type I LVTTL SPI-3 Input Data Word Modulo: These 2 inputs indicate the number of valid data bytes in ISPID(31- 0). The ISPIMOD bus should always be all zero, except during the last double-word transfer of a frame on ISPID(31-0) ...

Page 42

... MHz for SPI-3 emulation. O CMOS SPI-3 Output Data Bus: 32-bit bus used to transmit 12mA data to the Link Layer device. 8-bit SPI-3 Mode: OSPID(7-0); OSPID7 is MSB. 16-bit SPI-3 Mode: OSPID(15-0); OSPID15 is MSB. 32-bit SPI-3 Mode: OSPID(31-0); OSPID31 is MSB. Name/Function Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 43

... OSPITADR5 AB21 OSPITADR4 AE23 OSPITADR3 AD22 OSPITADR2 AC21 OSPITADR1 AB20 OSPITADR0 AF23 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - I/O/P* Type O CMOS SPI-3 Output Bus Parity: This output signal indicates 12mA the parity calculated over OSPID(31-0) bus. O CMOS SPI-3 Output Data Word Modulo: These 2 inputs ...

Page 44

... SPI-3 in Master mode I LVTTL SPI-3 Data Bus Width: SPI-3 Data Bus Width select 32-bit mode 01 - 16-bit mode 10 - 8-bit mode 11 - Reserved I LVTTL Configuration for CMACA (Configurable MAC A) Ports Ethernet interface mode select 00 - OFF GMII/MII Extended SMII SMII Name/Function Name/Function PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 45

... CFGCMACB1 A21 CFGCMACB0 B20 CFGCMACC1 C20 CFGCMACC0 D19 CFGCMACD1 A22 CFGCMACD0 B21 CFGUPMD A18 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Technical Characteristics - Type I LVTTL Configuration for CMACB (Configurable MAC B) Ports 8 to 15: Ethernet interface mode select 00 - OFF GMII/MII Extended SMII SMII I LVTTL Configuration for CMACC (Configurable MAC C) ...

Page 46

... DD1.8 V -0.3 3.9 DD3.3 V -0.5 5 -55 150 Level 100 % ESD absolute value 2000 LU V ALUES Conditions V Notes Notes Note 5 C Note ft/min. linear airflow Per IPC/JEDEC J-STD-020B Note 2 Non-condensing V Note 3 Meets JEDEC STD-78 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 47

... Parameter Input leakage current Input capacitance 4.4.2 Input Parameters For LVTTLpu (internal pull-up resistor) Parameter Input current Input leakage current Input capacitance PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Selected Parameter Values - Min Typ Max - 15.6 - Min Typ Max 3.3 3.45 155 160 ...

Page 48

... Min Typ Max 2.4 0.4 8.0 -8.0 -10 10 Min Typ Max 2.4 0.2 0.4 12.0 -12.0 -10 10 Min Typ Max 2.4 0.2 0.4 16.0 -16.0 -10 10 Unit Test Conditions Unit Test Conditions - Unit Test Conditions - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 49

... Input leakage current Input capacitance 4.4.7 Input/Output Parameters For LVTTL/CMOS 16mA Parameter Input leakage current Input capacitance PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Selected Parameter Values - Min Typ Max 2.0 0.8 - 2.4 0.4 8.0 -8.0 Min Typ Max 2.0 0.8 - 2.4 0.4 16.0 -16 ...

Page 50

... SSYNCIN (Input) SSYNCOUTn (Output Parameter SMIIREFCLKn period SMIIREFCLKn duty cycle SSYNCIN setup time to SMIIREFCLKn SSYNCIN hold time from SMIIREFCLKn SSYNCOUTn delay from SMIIREFCLKn Timing Characteristics - - 5.0 T IMING Symbol Min 1 1 HARACTERISTICS t D Typ Max Unit PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 51

... TXmn (Output) Note Load on All Outputs Parameter TX delay from SMIIREFCLKn mn Figure 13. SMII Receive Interface Timing SMIIREFCLKn (Input (Input) Parameter RX setup to SMIIREFCLKn mn RX hold from SMIIREFCLKn PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - Symbol Min t 1 Symbol Min t 1 Envoy-CE4 Device ...

Page 52

... Envoy-CE4 Device DATA SHEET TXC-06885 Figure 14. GMII Transmit Interface Timing Using GmTXCLKI GmTXCLKI (Input) GmTXCLKO (Output) GmTXEN (Output) TXmn (Output) GmTXER (Output) Note load on GMII outputs Parameter GmTXCLKI duty cycle GmTXCLKI PERIOD GmTXCLKO duty cycle GmTXCLKO period GmTXCLKO (low to high transition time, ...

Page 53

... GmRXDV, RXmn, GmRXER setup to GmRXCLK Note: The GMII and MII Receive Interface Timing diagrams are specified together in 15, since they are the same. The GMII and MII Transmit Interface Timing diagrams are specified separately in PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - ...

Page 54

... Envoy-CE4 Device DATA SHEET TXC-06885 Figure 16. MII Transmit Interface Timing Using GmMTXCLK GmMTXCLK (Input) GmTXEN (Output) TXmn (Output) GmTXER (Output) Note load on GMII outputs Parameter GmMTXCLK duty cycle GmMTXCLK PERIOD GmMTXCLK (low to high transition time, 10% to 90%) GmTXEN, TXmn, GmTXER delay from ...

Page 55

... Figure 17. Management MII Interface Timing MDC (Output) MDIO (In/Out) Note load on all MII outputs Parameter MDC frequency MDC duty cycle MDIO delay from MDC MDIO setup to MDC MDIO hold from MDC PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - Symbol Min 1/t 1 ...

Page 56

... TSPITENB, ISPID(31-0), PRTY, SOP, EOP, MOD(1-0), ERR, TSX, ADR(7-0) hold from ISPICLK STPA, PTPA(7-0) delay from ISPICLK Timing Characteristics - - Please refer to OIF SPI-3 specification for protocol waveform. Symbol Min Typ Max Unit 1/t 25 125 MHz PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 57

... OSPIRVAL (Output) OSPIRSX (Output) Note load on SPI-3 interface outputs. Parameter OSPICLK frequency OSPICLK duty cycle OSPIRENB setup to OSPICLK OSPIRENB hold from OSPICLK OSPID(31-0), PRTY, MOD(1-0), ERR, SOP, EOP, VAL, RSX delay from OSPICLK PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - ...

Page 58

... TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay after TCK Timing Characteristics - - t H(1) t SU( Symbol Min 2.0 SU(1) t 3.0 H(1) t 1.0 SU(2) t 5.0 H( Typ Max Unit 23.0 ns PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 59

... Setup time of UPA to rising edge UPCLK Setup time of RDWR to rising edge UPCLK Setup time rising edge UPCLK Setup time of falling edge WRDS to rising edge UPCLK Setup time of UPD to rising edge UPCLK Hold time of UPA to rising edge UPCLK PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - SU5 ...

Page 60

... Only applies if a write access is followed by a read access. RDWR may stay low between 2 successive write accesses to the same peripheral. g. Timing is relative to the rising edge before the one during which DTACK is asserted Timing Characteristics - - Symbol Min Typ Max Unit - 15.0 ns 7 Cycles PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 61

... Setup time of UPA to rising edge UPCLK Setup time of RDWR to rising edge UPCLK Setup time rising edge UPCLK Setup time of falling edge WRDS to rising edge UPCLK Hold time of UPA to rising edge UPCLK Hold time of RDWR to rising edge UPCLK PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - ...

Page 62

... Timing is relative to the rising edge before the one during which DTACK is asserted Timing Characteristics - - Symbol Min 15.0 SU6 d t 3.0 H6 Typ Max Unit - 20.0 ns 7 Cycles - ns 12.0 ns PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 63

... Assertion time for WRDS (Write Strobe) Write completion to DTACK going low UPD, UPA, CS hold time to DTACK going low CS inactive hold time after write completion (for back to back writes or reads) Note: The microprocessor clock must be present for correct operation. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Timing Characteristics - ...

Page 64

... UPD, UPA, CS hold time to DTACK going low CS inactive hold time after read completion (for back to back reads or writes) Note: The microprocessor clock must be present for correct operation Timing Characteristics - - Symbol Min in Max in UPCLK UPCLK Cycles Cycles PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 65

... Bit 25). When the IFIFO is configured for Store and Forward mode, the frame is discarded and will not show up on the SPI port. When the IFIFO is configured for Streaming mode, a bad FCS is appended to the frame. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - 6.0 O ...

Page 66

... Total number of bytes received. This counter can be programmed to exclude byte counts from errored frames (40 bit) • Total number of frames received. This includes errored frames (32 bit) • Count of Multicast frames received (32 bit) • Count of Broadcast frames received (32 bit) • Count of PAUSE Control frames received (32 bit Operation - - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 67

... Ingress FIFO (or channel selection) for frame reads, is done by the SPI-3 interface. For SPI-3, the selection is done by the scheduler in the Envoy-CE4 SPI-3 interface block. The scheduler uses a round robin selection scheme. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - 76. If the Ethernet device transmitting frames, ignores the backpressure “ ...

Page 68

... Note: The following figures show the inclusion of the FCS. Standard Ethernet Frame at SMII/GMII interface Preamble Start of Frame (7 bytes) Delimiter (1 byte Operation - - Destination Source Length/ Address Address Type (6 bytes) (6 bytes) (2 bytes) Data Frame Check (46 to 1500 Sequence bytes) (4 bytes) PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 69

... SPI-3 error pin asserted are discarded and will not show up on the Ethernet port. When the egress FIFO is configured for Streaming mode, frames received with the SPI-3 error pin asserted will show up on the Ethernet port with an additional four bytes of bad CRC appended to it. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - Source ...

Page 70

... SPI-3 Master will never raise its ISPIRENB output. Setting this bit shuts off all Rx backpressure reporting from the Envoy-CE4. If the Oversubscription enable bit is set to ‘0’, the SPI-3 Master uses the ISPIRENB output pin to exert standard SPI-3 backpressure Operation - - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 71

... Egress FIFO and a count of the discarded frames are provided per channel. Note: The discard frame count is used to count frames discarded due to an Egress FIFO overflow condition and the SPI-3 Error pin assertion condition. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - Destination ...

Page 72

... The MAC provides the option to append the correct FCS when Ethernet frames presented to the Envoy-CE4 at the SPI-3 Input interface, do not contain a valid FCS. Please note that this option also works in conjunction with the pad option Operation - - PRELIMINARY TXC-06885-MB, Ed. 6A “Ethernet Full Duplex” on February 2005 ...

Page 73

... The MAC records the following statistics using counters that are programmable as either clear on read saturating counters or rollover counters (Register 0x0030 Bit 0). • Total number of bytes transmitted. This counter can be programed to exclude byte counts from errored frames (40 bit) PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - Envoy-CE4 Device ...

Page 74

... SPI-3 port 0 onto multiple Ethernet ports. The port number is assigned from and a byte of packet data is used to convey this information. The appended port number will be removed before transmission onto the appropriate Ethernet interface Operation - - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 75

... Binary Exponential Backoff” (BEB) algorithm. Following this backoff time, the frame is retried. When enabled, the “No Backoff” configuration bit (Register 0x400C Bit 17) retransmits the frame without a backoff, following a collision. This option needs to be enabled with caution. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - ...

Page 76

... PAUSE control frame is paused. The Flow control operation in the Envoy-CE4 is divided into two operations: 1) The action taken when a PAUSE control frame is received from a remote device Operation - - th retransmission attempt is chosen as a uniformly where k = min(n,10). So, after the first PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 77

... Envoy-CE4 will transmit a PAUSE control frame with a pause_time value of zero to the remote device held in the pause state. The PAUSE control frame with pause_time value of zero will initiate resumption of transmission of data frames from the remote device to the Envoy-CE4. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Operation - Envoy-CE4 Device ...

Page 78

... Envoy-CE4, when the Ingress FIFOs reach the High Watermark and also generate a PAUSE control frame with a null value for pause_time, when the Ingress FIFO reaches the Low Watermark. This allows the Host to regulate the flow control mechanism Operation - - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 79

... Configuration for Port 1 to Port 31 and for register addresses for Ethernet statistics for Port 1 to Port 31. The SMIIREFCLK for each of the four CMACs must be active for these registers to operate correctly - even when the CMAC is configured in GMII mode. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - ...

Page 80

... Reserved IrqMask Reserved IrqStatus Reserved CfgPins Reserved Reserved StatIrqStatus StatIrqMask Reserved MII MGMT Configuration MII MGMT Command MII MGMT Address MII MGMT Control MII MGMT Status MII MGMT Indicators - 8 7 ResetControl IrqMask IrqStatus * Reserved GlobalCon trol PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 0 ...

Page 81

... Memory Maps and Bit Descriptions - Description Reserved TXC Manufacturing ID: This field contains the manufacturer identification number for TranSwitch Corporation, which is 0x06B. ENVOY ID: This field contains the Envoy-CE4 part number, TXC-06885. Device Version Level. This field is 1. Reserved processor. Reserved Reset Ethernet Port 0: Writing this bit will reset the Ethernet Port ...

Page 82

... Ethernet Port 1. Writing this bit will enable interrupts from Ethernet Port 1. Interrupt Mask for Ethernet Port 31: Writing this bit will mask the interrupt from Ethernet Port 31. Writing this bit will enable interrupts from Ethernet Port 31. - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 83

... PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Interrupt Mask for Ingress FIFO: Writing this bit will mask the interrupt from the Ingress FIFO. Writing this bit will enable interrupts from the Ingress FIFO. Interrupt Mask for SPI-3 Output Interface: Writing this bit will mask the interrupt from the SPI-3 output interface ...

Page 84

... Extended SMII SMII CMAC B Pin Configuration: Reflection of the Configuration Pin for configuring MAC B (Pin - CFGCMACB[1-0 OFF GMII/MII Extended SMII SMII CMAC C Pin Configuration: Reflection of the Configuration Pin for configuring MAC C (Pin - CFGCMACC[1-0 OFF GMII/MII Extended SMII SMII - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 85

... PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description CMAC D Pin Configuration: Reflection of the Configuration Pin for configuring MAC D (Pin - CFGCMACD[1-0 OFF GMII/MII Extended SMII SMII Reserved SPI-3 INPUT MODE Pin Configuration: Reflection of the Configuration Pin for configuring the SPI-3 Input Mode (CFGISPIMD) ...

Page 86

... Ethernet Statistics block for Ethernet Port 0. Interrupt Status for Ethernet Ports Ethernet Statistics Interrupt Mask for Ethernet Port 0 Ethernet Statistics masks the interrupt from the Ethernet Statistics block for Ethernet Port 0. Interrupt Mask for Ethernet Ports Ethernet Statistics Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 87

... RO 31-7 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description MII MGMT: CONFIGURATION REGISTER MGMT Clock Select: This field determines the clock frequency of the MGMT Clock (MDC). Consult Table below - MGMT Clock Select Encoding on how to program this field. MGMT Clock Select Encoding ...

Page 88

... Reserved MII MGMT: Data Write MII MGMT Write: When written, an MII MGMT write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII MGMT Address Register (0x0048). Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 89

... 31-1 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description MII MGMT: Data Read MII MGMT Read Data: Following an MII MGMT Read Cycle, the 16-bit data can be read from this location. MII MGMT Read Register Address: Following an MII MGMT Read Cycle, the 5-bit register address of the register that was accessed can be read from this location ...

Page 90

... SPI-3 Input STPA High Threshold SPI-3 Input PTPA Low Threshold SPI-3 Input PTPA High Threshold SPI Input Error Status SPI-3 Input Interrupt Mask SPI-3 Output Config SPI-3 Output STPA Threshold SPI-3 Output Burst Size STPAEN PTPAEN PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 0 ...

Page 91

... Reserved 27B8 Reserved 27BC 27C0 27C4 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - 16 15 Per Port Egress FIFO Disabled Error Status Per Port Egress FIFO Start of Packet Error Status Reserved Per Port Egress FIFO Full Interrupt Mask ...

Page 92

... Egress FIFO will de-assert STPA. The value is specified in terms of the SPI-3 bus width. For a bus width of 8 bits, the value is based on bytes. For a bus width of 16 bits, 2 bytes and a bus width of 32 bits, 4 bytes. Minimum value is 2. Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 93

... RO 31-4 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description SPI-3 Input PTPA Low Threshold: Input SPI-3 near full low threshold for assertion of PTPA. Once the PTPA is de-asserted because the Egress FIFO reached the SPI-3 high threshold (SIPHT), PTPA will be asserted when the Egress FIFO reaches the PTPA low threshold ...

Page 94

... SPI-3 Ingress Packet Errors indicated over the SPI-3 Error pin for Port 1. Clear on Read SPI-3 Input Packet Error Counter Port 31: Counter indicating the number of SPI-3 Ingress Packet Errors indicated over the SPI-3 Error pin for Port 31. Clear on Read. - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 95

... RW 7-0 00000000 RO 31-8 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description SPI-3 Base Address: The 3 bit base address used to create the 8 bit SPI-3 port address for both SPI-3 Input and SPI-3 output. The base address bit programmable value and is assigned to the most significant 3 bits of the 8 bit SPI-3 address ...

Page 96

... Start of Packet and End of Packet in the same word (b) Assertion of the SPI-3 Error pin after a start of packet has been received. (c) An overflow occurred in the Egress FIFO. Packets are dropped in store and forward mode only (Egress FIFO Mode = 0). Clear on Read. - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 97

... FFFFFFFF Egress FIFO Disabled Error Interrupt Mask Per Port: Disabled 254C RW 31-0 FFFFFFFF Egress FIFO Start of Packet Error Interrupt Mask Per Port: Egress PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description . . Egress FIFO Packet Drop Counter Port 31: The Egress FIFO Packet ...

Page 98

... Reserved When the Port is in Streaming mode and the Egress FIFO reaches the programmed threshold, an indication is sent to the associated Configurable MAC block to transfer the Port’s Packet Data across the Ethernet interface. Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 99

... RC 31-0 00000000 2704 RC 31-0 00000000 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description . . Egress FIFO Streaming Threshold Port 31: Egress FIFO Streaming threshold in bytes for Port 31. The values are: 000 - 64 Bytes 001 - 128 Bytes 010 - 256 Bytes ...

Page 100

... Pause frames will halt or raise carrier will be de-asserted from that port. Note: Automatic pause frame generation needs to be enabled. Pause frame generation state is reached once the Pause high threshold is crossed. Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 101

... RW 12-0 1FFF RO 31-13 0 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Flow Control High Threshold CMAC B: This register sets the high threshold in multiples of 8 bytes, for Ports (serviced by Configurable MAC B), for generation of PAUSE frames or asserting raise carrier. In the event one of the Ethernet port’s ingress FIFO (serviced by Configurable MAC B) reaches this threshold, a Pause frame will be sent or raise carrier will be asserted from that port ...

Page 102

... Frame Regeneration time sets the time between consecutive Pause frames from an ethernet port, while the port is in the Pause Generation state. Note: Pause frame generation state is reached once the Pause high threshold is crossed and the Pause low threshold is not reached. Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 103

... FFFFFFFF Ingress FIFO Near Full Interrupt Mask Per Port: FIFO Near full 27C4 RW 31-0 FFFFFFFF Ingress FIFO PHY/Port Enable Per Port: Ingress FIFO/Port Enable PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Pause Frame Regeneration Timer CMAC C: This register sets the Pause frame regeneration time in Pause Quanta (1 Pause Quanta = 512 bit times) for ports 16 to 23, (serviced by Configurable MAC C) ...

Page 104

... IPG / IFG Half-Duplex Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Source Address 1-4 Reserved IrqMask Reserved Reserved - 8 7 Maximum Frame Length Test Register SMII Status Reserved Reserved CFPT LocCtrl2 IrqStatus Reserved PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 0 GMII/ SMII ...

Page 105

... PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - 79. Description Port 0 MAC Configuration and Status Registers. Port 0 Configuration Register #1 Transmit Enable Transmission of frames is prevented 1 - The port is allowed to transmit frames to the system Synchronized Transmit Enable Transmit Enable is synchronized to the transmit stream ...

Page 106

... Note: Used for frames transmitted from the Ethernet (Egress) ports only Reserved Length Field Checking length field checking is performed 1 - The port will check if the frame length field matches the actual data field length - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 107

... RO 31-16 4008 RW 6-0 0x60 RO 7 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Huge Frame Enable The port will limit the length of frames to the Maximum Frame Length value 1 - Allows frames longer than the Maximum Frame Length to be transmitted and received ...

Page 108

... Its range of values is 0x0 to IPG2. Default value is 0x40 (64d) which follows the two-thirds/one-third guideline. Note: For an IPG length of 96 and a 2/3 ratio, the values 0x20 and 0x7C are required in the IPG1 and IPG2 locations, respectively. Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 109

... 23-20 0xA RO 31-24 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description HALF-DUPLEX REGISTER Collision Window: This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD are included ...

Page 110

... Allows MAC-to-PHY connections where Envoy-CE4 connects to a PHY Reserved Reset SMII Port: This resets the port configured as an SMII port. SMII STATUS REGISTER Reserved Speed The Serial MII PHY is operating at 10 Mbit/s mode 1 - The Serial MII PHY is operating at 100 Mbit/s mode - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 111

... RO 31-0 to 407C PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Full Duplex The Serial MII PHY is operating in Half-Duplex mode 1 - The Serial MII PHY is operating in Full-Duplex mode Link OK The Serial MII PHY has not detected a valid link ...

Page 112

... Disable 1 - Enable Note: Set Flow Control Mode (Bit 30) to Raise Carrier or PAUSE frame depending whether the Port is in half duplex or full duplex. STEN: Statistics Enable Disables internal statistics counters update 1 - Enables internal statistics counters to update Reserved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 113

... PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Tx Source Address Substitute Enable: Transmitter Source Address Substitution Enable Substitute the outgoing source address field in the Ethernet header with the programmed source address in the MAC (Addresses 0x4040 and 0x4044). Rx CRC Remove: Configures the removal of the CRC (FCS) bytes from the Ethernet frame received at the Rx interface destined for the SPI-3 output interface ...

Page 114

... Flow Control Mode: Configures the flow control mode Raise Carrier Mode 1 - Pause Frames Half-Duplex Flow Control Duration: Configures the Half Duplex flow control duration Raise Carrier stopped after 128K byte times 1 - Continuous Raise Carrier flow control till congestion is relieved - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 115

... Depends on CMAC Configurati on pins 31-2 0 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Reserved PAUSE Frame Received: Status indication that an error free, unicast, or multicast PAUSE frame has been received. Rx Frame Discarded: Status indication of a frame discard due to lack of FIFO memory resource (overflow) ...

Page 116

... FCS octets). Rx 512 to 1023 Octet Packets: The total number of packets (including bad packets) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including FCS octets). - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 117

... RC 31-0 0 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Rx 1024 to 1518 Octet Packets: The total number of packets (includ- ing bad packets) received that were between 1024 and 1518 octets (1522 for VLAN tagged packets) in length inclusive (excluding framing bits but including FCS octets) ...

Page 118

... Note: Packets less than 64 octets but with a bad FCS are counted in the Tx Fragment Packets counter Octet Packets: The total number of packets (including bad pack- ets) transmitted successfully that were 64 octets in length (excluding framing bits but including FCS octets). - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 119

... RC 31-0 0 6088 RC 31-0 0 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description 127 Octet Packets: The total number of packets (including bad packets) transmitted successfully that were between 65 and 127 octets in length inclusive (excluding framing bits but including FCS octets). ...

Page 120

... FCS octets), and had a bad Frame Check Sequence (FCS). This count will include packets truncated by the MAC because they were longer than MAX octets. MAX octets value is the “Maximum Frame Length” value programmed in the MAC. - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 121

... RC 7 31-8 0 PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - Memory Maps and Bit Descriptions - Description Tx Drop Frame: The total number of transmitted packets which were aborted due to an under-run of the Egress FIFO, i.e., lack of system resources. When this is detected, the MAC transmitter will jam the packet and insert an incorrect FCS ...

Page 122

... Envoy-CE4 Device DATA SHEET TXC-06885 The Envoy-CE4 device is packaged × 27 mm, 580-Lead Plastic Ball Grid Array (PBGA) package with a 1.0 mm pitch, as illustrated in TRANSWITCH TXC-06885BIOG TXC-06885BROG D D2 E1/4 D1 Notes: 1. All dimensions are in millimeters. Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone ...

Page 123

... Part Number: TXC-06885BIOG 580-lead plastic ball grid array (PBGA) package, TXC-06885BROG 580-lead plastic ball grid array (PBGA) package, ® PHAST -12P Device (STM-4/OC-12 SDH/SONET Overhead Terminator with CDB/PPP UTOPIA/POS-PHY Interface). The PHAST-12P is a highly integrated SDH/SONET overhead terminator device designed for ATM cell and PPP packet payload mappings. A single PHAST-12P can terminate four individual STM-1/OC-3 lines or a single STM-4/OC-12 line ...

Page 124

... Fax: 20 7417 7500 Tel: Fax: 3 3438 3698 Tel: Tel: Fax: (303) 397-2740 Web: Tel: Fax Web: S OURCES (212) 642-4900 www.ansi.org (415) 561-6275 www.atmforum.com 20 7837 7882 3 3438 3694 (800) 854-7179 (within U.S.A.) (303) 397-7956 (outside U.S.A.) www.global.ihs.com www.etsi.org PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 125

... Corporate Place Rm 3A184 Piscataway, NJ 08854-4157 TTC (Japan): TTC Standard Publishing Group of the Telecommunication Technology Committee Hamamatsu-cho Suzuki Building 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 Envoy-CE4 Device DATA SHEET TXC-06885 Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) ...

Page 126

... Envoy-CE4 Device DATA SHEET TXC-06885 NOTES - PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 ...

Page 127

... TranSwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PRELIMINARY TXC-06885-MB, Ed. 6A February 2005 - NOTES - Envoy-CE4 Device ...

Page 128

... VLSI semiconductor solutions to communications network equipment manufacturers. Serving three fast-growing end-markets; Public Network Infrastructure, Internet Specializing in the design, development, marketing and support of these networking semiconductor solutions, which we call TranSwitch Corporation • 3 Enterprise Drive Tel: 203-929-8810 • Infrastructure and Wide Area Networks (WANs). ...

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