TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 127

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 2 7 o f 2 02
11.10.1 Transmit High Order POH Port Interface
Note the address corresponding to the master VC is used for concatenated structures. E.g.,
when mapping four VC-4/STS-3c’s SPE in a STM-4/OC-12, only 0x0, 0x3, 0x6 and 0x9 will
be valid values for A[7:4].
The transmit High Order POH port interface allows inserting most High Order Path Overhead
bytes into the High Order POH. J1 and C2 cannot be selected from the transmit High Order
POH port interface, while the B3 BIP-8 can be used as error mask on the calculated BIP-8 for
test purposes.
The Transmit POH Port consists of following leads:
The Transmit POH Port protocol is as follows (see
Note: No configuration is necessary for the Transmit POH Port. The source of the POH bytes
can be configured in the memory map of the POH Generator (see
• Output Transmit POH Port Clock POHTXCLK
• Output Transmit POH Port Address Latch Enable POHTXALE
• Output Transmit POH Port Address POHTXADDR
• Output Transmit POH Port Data Latch Enable POHTXDLE
• Input Transmit TOH Port Data POHTXDATA
A7
1
1
1
1
1. The 8-bit address for the requested byte is output on POHTXADDR, most significant
2. A one cycle gap is left open.
3. The Data Latch Enable POHTXDLE is asserted and the 8-bit data word is sampled on
- High Order Pointer Tracking, Retiming and Pointer Generation -
bit first. During this time the Address Latch Enable POHTXALE is asserted.
the input POHTXDATA, most significant bit first.
A6
1
1
1
1
A5
0
0
1
1
A4
0
1
0
1
NA
NA
NA
NA
Figure
Assigned to
11):
PRELIMINARY TXC-06312B-MB, Ed. 2
Table
PHAST-12N Device
82).
DATA SHEET
TXC-06312B
June 2005