TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 179

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 7 9 o f 2 02
Offset
0x000C 1 - 0
0x000A 0
0x000E 1 - 0
0x001E
0x0000 0
0x0002 2 - 0
0x0004 0
0x0006 0
0x0008 0
0x0010 4-0
0x0012 4-0
0x0014
Bits
TimingMode
LineTimingChannel
TxRefSelect
RxRefSelect
TxPLL_Cap_Enable
RxPLL_Cap_Enable
TxRefFreq
RxRefFreq
TxPLL_PowerDown
RxPLL_PowerDown
CDRTune
PLLTune
Name
- Memory Maps and Bit Descriptions -
Init
0x1F Power Down for the Transmit PLL modules.
0x1F Power Down for the RxPLL modules.
Table 55: PLL Control
0x0 External/Line timing mode selection for the transmit PLL.
0x0 range 0 to 4
0x0 Transmit reference clock external source selection for the PLL in the transmit section.
0x0 Receive reference clock external source selection for the PLL in the receive section.
0x0 Enables the external capacitor in the Transmit PLL when 0x1.
0x0 Reserved. Must be set to 0.
0x0 Transmit PLL reference clock frequency.
0x0 Receive PLL reference clock frequency.
External timing mode is selected when 0x0, TxRefSelect selects the external source.
Line-Timing mode is selected when 0x1, LineTimingChannel selects the line timing
channel.
Line timing mode channel selection.
This field is only used when TimingMode is ‘1’. The value indicates the line.
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This field is only valid when TimingMode is ‘0’.
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Indicates the frequency of the reference clock for the PLL.
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Indicates the frequency of the reference clock for the PLL.
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Must be set to 0x0 at power-up.
Must be set to 0x0 at power-up.
Array (5) of T_CDRTune
Offset between two elements = 0x2.
Array index indicates the interface.
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T_PLLTune
0x0: Line 1
0x1: Line 2
0x2: Line 3
0x3: Line 4
0x4: APS
0x0: REFTXCLK1 is used as reference clock
0x1: REFTXClK2 is used as reference clock
0x0: REFRXCLK is used as reference clock
0x1: REFTXCLK1/REFTXCLK2 is used as reference clock, the selection
between the transmit reference clocks is made using the TxRefSelect field
0x0: 19.44 MHz, REFTXCLK1 or REFTXCLK2
0x1: 77.76 MHz, REFTXCLK1 or REFTXCLK2
0x2: 155.52 MHz, REFTXCLK2
0x3: 622.04 MHz, REFTXCLK2. In this mode the Transmit PLL must be
bypassed. Mind the Transmit PLL is actually still working then, although it’ s out-
put is never used.
0x0: 19.44 MHz, REFRXCLK or REFTXCLK1 or REFTXCLK2
0x1: 77.76 MHz, REFRXCLK or REFTXCLK1 or REFTXCLK2
0x2: 155.52 MHz, REFTXCLK2
0x3: Reserved
Array index 0: Line 1
Array index 1: Line 2
Array index 2: Line 3
Array index 3: Line 4
Array index 4: APS
(See page
180)
(T_PLL_Control)
(See page
180)
Description
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005