TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 49

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4 9 o f 2 0 2
LVDS I/O RECOMMENDATIONS:
LVDS - APS Port:
The LVDS I/O on the APS Port (APSRXDATAP/N, APSTXDATAP/N) is compliant to the LVDS
standard: [IEEE Std 1596.3-1996].
The LVDS receiver (APSRXDATAP/N) has an integrated 100
P and N. It is however recommended to provide a 100
APSRXDATAP and APSRXDATAN, as close as possible to the PHAST-12N. This resistor will
normally be treated as ‘do not install’.
Use DC coupling (no series capacitors).
LVDS - PCB, Connector and Cable guidelines:
The differential pairs (P and N) will be routed together, have a controlled impedance of 50
and be the same length. Make them as short as possible and in as straight a path as
possible. Vias should be avoided if practicable.
Use high quality connectors that are qualified for an LVDS signal at 622.08 Mbit/s (311.04
MHz).
The APS Port always operates at this rate. It cannot operate at a lower rate.
When a cable is used to interconnect two PHAST-12N devices using the APS Port, it is
mandatory to use a 50
meter.
It is required to have a common ground between the two PHAST-12N devices that are
connected using the APS Port.
LVDS - Unused pins:
Unused LVDS inputs can be left floating (no resistors required).
Unused LVDS outputs can be left floating (no resistors required).
- Selected Parameter Values -
cable. In a careful implementation, cable length can be up to 2
resistor on the board, between
PRELIMINARY TXC-06312B-MB, Ed. 2
termination resistor between
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005