TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 169

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1 6 9 o f 2 02
Offset
Offset
Offset
0x0400
0x0000 0
0x0000 0
1
Bits
Bits
Bits
TOH_Contents
TOH_Port_Enable
RSOH_DCC_Select
DCC_Port_Enable
Table 33: Receive TOH Port Configuration
Table 34: Receive DCC Port Configuration
Name
Table 32: Receive TOH and DCC Port
Name
Name
- Memory Maps and Bit Descriptions -
All 0x0 ro
Init
Access
Init
Init
0x0 TOH Port is enabled when 0x1.
0x0 Select mode for DCC port. The DCC port sends RS DCC bytes (D1-
0x0 The DCC port is enabled when 0x1 and the
D3) when 0x1 and MS DCC bytes (D4-D12) when 0x0. Only valid
when the DCC port is enabled.
RSOH_DCC_Port_Select setting determines which set of DCC
bytes will be sent out on the DCC port (RS DCC or MS DCC).
Array (324) of byte
Offset between two elements = 0x2.
Array index indicates the TOH byte number.
Received TOH bytes (raw, unprocessed values, except B1/B2).
The order in which bytes are mapped in memory is the same order
as these bytes appear in the TOH. For STM-1 mode the columns
are byte interleaved: column #1 corresponds to line 1, column 2 to
line 2, etc.
The byte number can easily be calculated as follows: byte number
= (a-1)x36 + (b-1)x4 + c-1
where
See also [ITU-T G.707/Y.1322] for the TOH bytes locations.
Note: B1 and B2 locations contain the EXOR of the calculated BIP
with the received BIP.
• a = row number (1 to 9)
• b = multi-column number (1 to 9)
• c, for STM-4 mode = depth of the interleave within the multi-
• c, for STM-1 mode = line number (1-4)
column (1-4)
(T_RX_TOH_DCC_PORT)
(T_RXTDP_Common_Config)
(T_RXTDP_Line_Config)
Description
Description
Description
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005