ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 96

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 6 Clock Generation Circuit
6.4 Specifying Port Registers
6.4.1
To enable the clock output function, each related port register bit needs to be set. See Chapter 15, "Port 2" for
detail about the port registers.
Set P21MD bit (bit1 of P2MOD register) to “1” for specifying the high-speed clock output as the secondary function of
P21.
Set the P21C1 bit (P2CON1 register's bit 1) to "1" and the P21C0 bit (P2CON0 register's bit 1) to "1" for specifying the
state mode of the P21 pin to CMOS output.
The P21D bit (P2D register bit 1) data can either be "0" or "1".
- : Bit that does not exist
* : Bit not related to the high-speed clock function
** : Don’t care
Note:
P21 (Port 2) is an output-only port and does not have the register to select the data direction(input or output).
Bit name
Bit name
Bit name
Bit name
Register
Register
Register
Register
Setting
Setting
Setting
Setting
name
name
name
name
Functioning P21 (OUTCLK) as the high-speed clock output
value
value
value
value
Bit
Bit
Bit
Bit
7
7
7
7
-
-
-
-
-
-
-
-
6
6
6
6
-
-
-
-
-
-
-
-
5
5
5
5
-
-
-
-
-
-
-
-
P2CON1 register (Address: 0F213H)
P2CON0 register (Address: 0F212H)
P2MOD register (Address: 0F214H)
P2D register (Address: 0F210H)
6-10
4
4
4
4
-
-
-
-
-
-
-
-
3
3
3
3
-
-
-
-
-
-
-
-
P22MD
P22C1
P22C0
P22D
2
2
2
2
*
*
*
*
P21MD
P21C1
P21C0
P21D
**
1
1
1
1
1
1
1
P20MD
P20C1
P20C0
P20D
0
0
0
0
*
*
*
*