ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 158

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ML610Q409-NNNTBZ03A7

Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r

Specifications of ML610Q409-NNNTBZ03A7

Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
PWM0* (Negative
PWM0* (Positive
After the P0RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1
clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed.
Figure 10-2 shows the operation timing of PWM0.
Note:
Write PW0CH
Write PW0CL
Even if “0” is written to the P0RUN bit, counting operation continues up to the falling edge (the PWM0 status flag
(P0STAT) is in a “1” state) of the next PWM clock pulse. Therefore, the PWM0 interrupt (PW0INT) may occur.
PW0DBUF
PW0PBUF
PW0CH/L
PW0DH/L
PW0PH/L
P0STAT
PW0INT
P0RUN
P0FLG
PW0CH/L
P0CK
logic)
logic)
P0STAT
P0RUN
P0FLG
P0CK
XXXX
2000 2001 2002 2003
Figure 10-2 (1/2) Operation Timing Diagram of PWM0
Figure 10-2 (2/2) Operation Timing Diagram of PWM0
A000
A000
0000
8000
8000
0001 0002
7777
BBBB
T
PWD
10-9
7FFF 8000 8001
2004
ML610Q407/ML610Q408/ML610Q409 User's Manual
T
PWP
BBBB
A000
7777
8000
8002
2005
A000 A000 0000 0001
2006
BBBB
7777
A000
8000
2007 2008
7777
BBBB
Chapter 10 PWM

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