ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 327

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2.7 Display Allocation Register B (DS39C4B to DS49C7B)
Address: 0F600H to 0F627H, 0F640H to 0F667H, 0F680H to 0F6A7H, 0F6C0H to 0F6E7H, 0F700H to 0F727H
Access: R/W
Access size: 8-bit
Initial value: Undefined
DSmCnB (m= 0 to 39, n = 0 to 4) are special function registers (SFRs) to store segment allocation data.
Each valid bit of DSmCnB becomes undefined at system reset.
Table 22-4 shows a list of the display allocation register B.
[Description of Bits]
Initial value
DSmCnB
•
R/W
b2-b0 (bit 2 to 0)
The b2 to b0 bits of DSmCnB (m = 0 to 39, n = 0 to 4) are used to set the bits of the display registers (DSPR00
to 27) that are output to common n of segment m.
Set DSmCnB when the DASN bit of the display control register 0 (DSPCON0) is "0".
When the DASN bit is “1”, access from the CPU is invalid.
b2
0
0
0
0
1
1
1
1
R/W
—
7
0
b1
0
0
1
1
0
0
1
1
R/W
—
6
0
b0
0
1
0
1
0
1
0
1
Selects bit 0
Selects bit 1
Selects bit 2
Selects bit 3
Selects bit 4
Selects bit 5
Selects bit 6
Selects bit 7
R/W
—
5
0
22-15
R/W
—
0
4
ML610Q407/ML610Q408/ML610Q409 User's Manual
R/W
Description
—
0
3
R/W
b2
2
x
Chapter 22 LCD Drivers
R/W
b1
1
x
R/W
b0
0
x