ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 81
ML610Q409-NNNTBZ03A7
Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q407P-NNNTB03A7.pdf
(33 pages)
3.ML610Q407P-NNNTB03A7.pdf
(391 pages)
Specifications of ML610Q409-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q407P-NNNTB03A7 PDF datasheet #2
- ML610Q407P-NNNTB03A7 PDF datasheet #3
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- Download datasheet (2Mb)
ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 5 Interrupt
5.3.1
5.3.2
5.3.3
Reference:
For the MIE flag, Program Counter (PC), CSR, PSW, and ELEVEL, see “nX-U8/100 Core Instruction Manual”.
When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the
processing of program shifts to the interrupt destination.
When an interrupt is generated regardless of the state of MIE flag, the following processing is performed by hardware
and the processing of program shifts to the interrupt destination.
A software interrupt is generated as required within an application program. When the SWI instruction is performed
within the program, a software interrupt is generated, the following processing is performed by hardware, and the
processing program shifts to the interrupt destination. The vector table is specified by the SWI instruction.
(1) Transfer the program counter (PC) to ELR1
(2) Transfer CSR to ECSR1
(3) Transfer PSW to EPSW1
(4) Set the MIE flag to “0”
(5) Set the ELEVEL field to“1”
(6) Load the interrupt start address into PC
(1) Transfer PC to ELR2
(2) Transfer CSR to ECSR2
(3) Transfer PSW to EPSW2
(4) Set the ELEVEL field to “2”
(5) Load the interrupt start address into PC
(1) Transfer PC to ELR1
(2) Transfer CSR to ECSR1
(3) Transfer PSW to EPSW1
(4) Set the MIE flag to “0”
(5) Set the ELEVEL field to“1”
(6) Load the interrupt start address into PC
Maskable Interrupt Processing
Non-Maskable Interrupt Processing
Software Interrupt Processing
5-20
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