ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 138

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 9 Timer
9.3 Description of Operation
9.3.1
The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer
clocks (TnCK) that are selected by the Timer 0 to 3 control register 0 (TMnCON0) when the TnRUN bits of timer 0 to 3
control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling.
When the count value of TM0 to TM3C and the timer 0 to 3 data register (TMnD) coincide, timer 0 to 3 interrupt
(TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting continues.
When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK).
Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 0–3 control register 1 (TMnCON1)
is “0”.
When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous values.
To initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (T
After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a
maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are
constant.
Figure 9-2 shows the operation timing diagram of Timer 0 to 3.
Note:
T
Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 3 status
flag (TnSTA) is in a “1” state) of the next timer clock pulse. Therefore, the timer 0 to 3 interrupt (TMnINT) may
occur.
TMI
Write TMnC
Timer mode operation
=
TnSTAT
TMnINT
(n=0∼3)
TnRUN
TMnC
TMnD
TnCK
TnCK (Hz)
TMnD + 1
TMnD:
TnCK:
XX
Figure 9-2 Operation Timing Diagram of Timer 0 to 3
Timer 0 to 3 data register (TMnD) setting value (01H to 0FFH)
Clock frequency selected by the Timer 0 to 3 control register 0 (TMnCON0)
TMI
00
) is expressed by the following equation.
88
(n=0 3)
01
T
TMI
02
9-20
87
88
88
00
01
5F
60
61
88
62