ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 103
ML610Q409-NNNTBZ03A7
Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q407P-NNNTB03A7.pdf
(33 pages)
3.ML610Q407P-NNNTB03A7.pdf
(391 pages)
Specifications of ML610Q409-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
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7.2.3
Address: 0F00BH
Access: R/W
Access size: 8-bit
Initial value: 00H
HTBDR is a special function register (SFR) to set the dividing ratio of the 4-bit, 1/n counter.
[Description of Bits]
*1: Indicates the frequency when the high-speed oscillation clock, HSCLK, is 500 kHz.
Initial value
•
HTBDR
R/W
HTD3-HTD0 (bits 3-0)
The HTD3-HTD0 bits are used to set the dividing ratio of the 4-bit, 1/n counter. The frequency divide ratios
selectable include 1/1 to 1/16.
HTD3
High-Speed Time Base Counter Divide Register (HTBDR)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R/W
−
7
0
HTD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R/W
−
6
0
HTD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
−
5
0
HTD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7-5
R/W
−
4
0
ML610Q407/ML610Q408/ML610Q409 User's Manual
1/16 (initial value)
1/15
1/14
1/13
1/12
1/11
1/10
1/9
1/8
1/7
1/6
1/5
1/4
1/3
1/2
1/1
Dividing ratio
HTD3
R/W
0
3
Description
HTD2
R/W
2
0
31kHz
33kHz
36kHz
38kHz
42kHz
45kHz
50kHz
56kHz
63kHz
71kHz
83kHz
100kHz
125kHz
167kHz
250kHz
500kHz
Chapter 7 Time Base Counter
Frequency of
HTBCLK (*1)
HTD1
R/W
1
0
HTD0
R/W
0
0
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