ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 56

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q40/7/ML610Q408/ML610Q409 User's Manual
Chapter 4 MCU Control Function
4.3 Description of Operation
4.3.1
4.3.2
The program run mode is the state where the CPU executes instructions sequentially.
At power-on reset, low-speed oscillation stop detect reset, WDT overflow reset, or RESET_N pin reset, the CPU
executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the
system reset mode is released.
At reset by the BRK instruction, the CPU executes instructions from the addresses that are set in the addresses 0004H
and 0005H of the program memory after the system reset mode is released. However, when the value of the interrupt
level bit (ELEVEL) of the program status word (PSW) is 02H or higher at execution of the BRK instruction (after the
occurrence of the WDT interrupt), the CPU executes instructions from the addresses that are set in the addresses 0002H
and 0003H.
For details of the BRK instruction and PSW, see the “nX-U8/100 Core Instruction Manual” and for the reset function,
see Chapter 3, “Reset Function”.
The HALT mode is the state where the CPU interrupts execution of instructions and only the peripheral circuits are
running.
When the HLT bit of the standby control register (SBYCON) is set to “1”, the HALT mode is set.
When a WDT interrupt request, or an interrupt request enabled by an interrupt enable register (IE1–IE7) is issued, the
HLT bit is set to “0” on the falling edge of the next system clock (SYSCLK) and the HALT mode is returned to the
program run mode released.
Figure 4-2 shows the operation waveforms in HALT mode.
Note:
Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt
processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”.
Program Run Mode
HALT Mode
Interrupt request
システムクロック
System clock
SBYCON.HLT
割込み要求
SYSCLK
CPUCLK
Program run mode
Figure 4-2 Operation Waveforms in HALT Mode
プログラム動作モード
4-10
HALT mode
HALT モード
プログラム動作モード
Program run mode