ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 77
ML610Q409-NNNTBZ03A7
Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q407P-NNNTB03A7.pdf
(33 pages)
3.ML610Q407P-NNNTB03A7.pdf
(391 pages)
Specifications of ML610Q409-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q407P-NNNTB03A7 PDF datasheet #2
- ML610Q407P-NNNTB03A7 PDF datasheet #3
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- Download datasheet (2Mb)
ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 5 Interrupt
5.2.14 Interrupt Request Register 5 (IRQ5)
Address: 0F01DH
Access: R/W
Access size: 8-bit
Initial value: 00H
IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ5 request flag is set to “1” regardless of the IE3 and MIE values when an interrupt is generated. In this case, an
interrupt is requested to the CPU when the related flag of the interrupt enable register (IE5) is set to “1” and the master
interrupt enable flag (MIE) is set to “1”.
By setting the IRQ5 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ5 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
Note:
Initial value
•
•
When an interrupt is generated by the write instruction to the interrupt request register (IRQ5) or to the interrupt
enable register (IE5), the interrupt shift cycle starts after the next 1 instruction is executed.
IRQ3
R/W
QTM2 (bit 4)
QTM3 (bit 5)
QTM2 is the request flag for the timer 2 interrupt (TM2INT).
QTM3 is the request flag for the timer 3 interrupt (TM3INT).
QTM2
QTM3
0
1
0
1
R/W
—
7
0
No request (initial value)
Request
No request (initial value)
Request
R/W
—
6
0
QTM3
R/W
5
0
5-16
QTM2
R/W
4
0
Description
Description
R/W
—
3
0
R/W
—
2
0
R/W
—
1
0
R/W
—
0
0
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