ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 210

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 13 UART
13.3.5 Receive Operation
Select the received data pin using the U0RSEL bit of the UART0UART0 mode register 0 (UA0MOD0). Select the
receive mode by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to "1". Then, set the U0EN bit of the
UART0 control register (UA0CON) to "1" to start receiving data.
Figure 13-6 shows the operation timing for reception.
When receive operation starts, the LSI checks the data sent to the input pin RXD0 and waits for the arrival of a start bit.
When detecting a start bit ( ), the LSI generates the internal transfer clock of the baud rate set with the start bit detect
point as a reference and performs receive operation.
The shift register shifts in the data input to RXD on the rising edge of the internal transfer clock. The data and parity bit
are shifted into the shift register and 5- to 8- bit received data is transferred to the transmit/receive buffer (UA0BUF)
concurrently with the fall of the internal transfer clock of
The LSI requests a UART0 interrupt on the rising edge of the internal transfer clock subsequent to the internal transfer
clock by which the received data was fetched ( ) and checks for a stop bit error and a parity bit error. When an error is
detected, the LSI sets the corresponding bit of the UART0 status register (UA0STAT) to “1”.
Parity error
Overrun error
Framing error
As shown in Figure 13-6, the rise of the internal transfer clock is set so that it may fall into the middle of the bit interval
of the received data.
Reception continues until the U0EN bit is reset to “0” by the program. When the U0EN bit is reset to “0” during
reception, the received data may be destroyed. When the U0EN bit is reset to “0” during the “U0EN reset enable period”
in Figure 13-6, the received data is protected.
: S0FER ＝“1”
: S0PER ＝“1”
: S0OER ＝“1”
13-16
.