ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 157

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 10 PWM
10.3 Description of Operation
The PWM0 counter registers (PW0CH, PW0CL) are set to an operating state (P0STAT is set to “1”) on the first falling
edge of the PWM clock (P0CK) that are selected by the PWM0 control register 0 (PW0CON0) when the P0RUN bit of
PWM0 control register 1 (PW0CON1) is set to “1” and increment the count value on the 2nd falling edge.
When the count value of PWM0 counter registers and the value of the PWM0 duty buffer (PW0DBUF) coincide, the
PWM flag (P0FLG) is set to “0” on the next timer clock falling edge of P0CK.
When the PW0CH and PW0CL count values match the PWM0 period buffer value, the P0FLG becomes "1" at the next
P0CK falling edge and the PW0CH and PW0CL are reset to 0000H to continue incremental counting. At the same time,
the value of the PWM0 duty register (PW0DH, PW0DL) is transferred to the PWM0 duty buffer (PW0DBUF) and the
value of PWM0 period register (PW0PH, PW0PL) to the PWM0 period buffer (PW0PBUF).
When the P0RUN bit is set to “0”, PWM0 counter registers stop counting after counting once the falling of the PWM
clock (P0CK). Confirm that PW0CH and PW0CL are stopped by checking that the PnSTAT bit of the PWM0 control
register 1 (PW0CON1) is “0”. When the P0RUN bit is set to “1” again, PWM0 counter registers restarts incremental
counting from the previous value on the falling edge of P0CK.
To initialize PWM0 counter registers to “0000H”, perform write operation in either of PW0CH or PW0CL. At that time,
P0FLG is also set to “1”.
When data is written in the PWM0 duty register (PW0DH, PW0DL) during count stop (P0RUN is in a “1” state), the
data is transferred to the PWM0 duty buffer (PW0DBUF) and when data is written in the PWM0 period register
(PW0PH, PW0PL), the data is transferred to the PWM0 period buffer (PW0PBUF).
The PWM clock, the point at which an interrupt of PWM0 occurs, and the logic of the PWM output are selected by
PWM0 control register 0 (PW0CN0).
The period of the PWM0 signal (T
equations.
T
T
PWP
PWP
PW0D:
PW0P:
P0CK:
=
=
PWM0 period registers (PW0PH, PW0PL) setting value (0001H to 0FFFFH)
PWM0 duty registers (PW0DH, PW0DL) setting value (0000H to 0FFFEH)
Clock frequency selected by the PWM0 control register 0 (PW0CON0)
P0CK (Hz)
P0CK (Hz)
PW0P + 1
PW0D + 1
PWP
) and the first half duration (T
10-8
PWD
) of the duty are expressed by the following