ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 333

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3.3 Segment Mapping When the Programmable Display Allocation Function is Used
When the programmable display allocation function is used (DASN bit of DSPMOD1 register is "1"), the segment map
of the display registers (DSPR00 to 27) can be programmatically changed using the display allocation registers (DSmCn:
m = 0 to 39, n = 0 to 4).
Figure 22-8 shows the configuration when using the programmable display allocation function.
In the display allocation register A (DSmCnA: m = 0 to 39, n = 0 to 4), set the address (00H to 27H) of the display
register (DSPR00 to DSPR27) that is output to the common n of the segment n. In display allocation register B
(DSmCnB: m = 0 to 39, n = 0 to 4), set the bits of the display register (DSPR00 to DSPR27) that is output to the
common n of the segment m.
For instance, to display bit 6 of display register 13 (DSPR13) to the common 3 of the segment 6, set as follows.
[Note]
- Set display allocation data to display allocation registers when the DASN bit of display mode register 1 (DSPMOD1) is
"0". When the DASN bit is “1”, access from the CPU is invalid.
"*" indicates an arbitrary value.
(0F4C6H)
0F527H
0F526H
0F402H
0F401H
0F400H
DS6C3A
Figure 22-8 Configuration When Using the Programmable Display Allocation Function
Data bus
Display allocation register A
DS39C4A
DS38C4A
DS2C0A
DS1C0A
DS0C0A
b7
*
6
Address specification of display register
b6
Specify the display
register's address
*
b5
0
b4
SEG1-COM0 mapping specification
SEG0-COM0 mapping specification
SEG2-COM0 mapping specification
1
SEG39-COM4 mapping specification
SEG38-COM4 mapping specification
b3
0
Display registers
b2
DSPR27
DSPR00
0
to
b1
1
22-21
b0
1
(0F6C6H)
DS6C3B
8
Display allocation register B
DS39C4B
DS38C4B
DS2C0B
DS1C0B
DS0C0B
Selector
3
b7
*
Specify the
display
register's bit
Bit specification of display register
b6
*
b5
0F727H
0F726H
0F602H
0F601H
0F600H
*
1
b4
*
Chapter 22 LCD Drivers
b3
*
Segment
Driver
b2
1
b1
1
b0
0
SEG39
SEG38
SEG2
SEG1
SEG0