ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 44

• Manufacturer Part Number: ML610Q409-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 4CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q409-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 3 Reset Function
3.2 Description of Registers
3.2.1
3.2.2
Address: 0F001H
Access: R/W
Access size: 8-bit
Initial value: Undefined
RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated.
At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is set
to ”1”. When checking the reset cause using this function, perform write operation to RSTAT in advance and initialize
the contents of RSTAT to “00H”.
[Description of Bits]
Note:
No flag is provided that indicates the occurrence of reset by the RESET_N pin.
Address
0F001H
Initial value
•
•
•
RSTAT
List of Registers
Reset Status Register (RSTAT)
R/W
POR (bit 0)
XSTR (bit 1)
WDTR (bit 2)
The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on.
The XSTR bit is a flag that indicates the generation of low-speed oscillation stop detect reset. When low-speed
oscillation stops for the period specified by the low-speed oscillation stop detection time (T
is set to “1”.
The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the
reset by overflow of the watchdog timer is generated.
WDTR
XSTR
POR
0
1
0
1
0
1
Reset status register
R/W
⎯
7
0
Power-on reset not generated
Power-on reset generated
Low-speed oscillation stop detect reset not occurred
Low-speed oscillation stop detect reset occurred
Watchdog timer reset not occurred
Watchdog timer reset occurred
Name
R/W
⎯
6
0
R/W
⎯
5
0
3-2
Symbol (Byte)
R/W
⎯
4
0
Description
Description
Description
RSTAT
R/W
⎯
3
0
Symbol (Word)
WDTR
R/W
—
2
0
XSTR
R/W
X
R/W
R/W
1
STOP
Size
) or more, this bit
8
POR
R/W
0
1
value
Initial
⎯