ML610Q409-NNNTBZ03A7 Rohm Semiconductor, ML610Q409-NNNTBZ03A7 Datasheet - Page 164

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ML610Q409-NNNTBZ03A7

Manufacturer Part Number
ML610Q409-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 4CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r

Specifications of ML610Q409-NNNTBZ03A7

Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ML610Q409-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
11. Watchdog Timer
11.1 Overview
11.1.1 Features
11.1.2 Configuration
This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in
order to detect an undefined state of the MCU and return from that state.
If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the
watchdog timer requests a WDT interrupt (non-maskable interrupt). When the second overflow occurs, the watchdog
timer generates a WDT reset signal and shifts the mode to a system reset mode.
For interrupts see Chapter 5, “Interrupt,” and for WDT interrupt see Chapter 3, “Reset Function”.
• Non-maskable interrupt
• Free running (cannot be stopped)
• One of four types of overflow periods (125ms, 500ms, 2s, and 8s) selectable by software
• Reset generated by the second overflow
Figure 11-1 shows the configuration of the watchdog timer.
WDTCON : Watchdog timer control register
WDTMOD : Watchdog timer mode register
WDTMOD
T256HZ
WDTCON
detection
Perform
“5AH”
Figure 11-1 Configuration of Watchdog Timer
WDT counter
detection
Perform
“0A5H”
R
WDT overflow
11-1
D
R
interrupt
QN
control
Q
Reset
WDP
RESET_S
System reset
WDT reset
WDTINT
Non-maskable interrupt
WDTCON Write
Data bus
Chapter 11 Watchdog Timer

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