ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 72

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4.2.3.2
Descriptor Statistic Mask (STATISTIC_MASK[0])
MSR Address
Type
Reset Value
Descriptor Statistic Mask (STATISTIC_MASK[1])
MSR Address
Type
Reset Value
72
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
31:0
Bit
Statistic Mask (STATISTIC_MASK[0:3]
Name
IOD_MASK
P2D_MASK
GLIU0: 100000A1h
GLIU1: 400000A1h
R/W
00000000_00000000h
GLIU0: 100000A5h
GLIU1: 400000A5h
R/W
00000000_00000000h
33234H
Description
Mask for Hits to Each IOD. Hits are determined after the request is arbitrated. A hit is
determined by the following logical equation: Hit = |(IOD_MASK[n-1:0] &
RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] &&
is_mem).
Mask for Hits to Each P2D. A hit is determined by the following logical equation: Hit =
|(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] &
RQ_DESC_HIT[n-1:0] && is_mem).
STATISTIC_MASK[0:3] Bit Descriptions
STATISTIC_MASK[0:3] Register Map
IOD_MASK
P2D MASK
Descriptor Statistic Mask (STATISTIC_MASK[2])
MSR Address
Type
Reset Value
Descriptor Statistic Mask (STATISTIC_MASK[3])
MSR Address
Type
Reset Value
GLIU0: 100000A9h
GLIU1: 400000A9h
R/W
00000000_00000000h
GLIU0: 100000ADh
GLIU1: 400000ADh
R/W
00000000_00000000h
AMD Geode™ LX Processors Data Book
9
8
7
GLIU Register Descriptions
6
5
4
3
2
1
0