ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 187

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR)
MSR Address
Type
Reset Value
L2_CONFIG_MSR controls the behavior of the L2 cache.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:24
23:20
19:16
15:9
Bit
8
7
6
5
4
3
2
1
0
Name
RSVD
L2_IM_LOCK
L2_DM_LOCK
RSVD
L2_TAG_
CLKGT_EN
L2_PASS_
IOMSR
L2_DMEVCT_
DIRTY
L2_WAIT_DM_
WR
L2_INVALID
L2_IM_ALLOC_
EN
L2_DM_ALLOC
_EN
L2_ALLOC_EN
L2_EN
RSVD
00001920h
R/W
00000000_0000000Eh
L2_IM_LOCK
Description
Reserved.
L2 Instruction Memory Subsystem Lock. On allocations from the IM, avoid using the
ways that have the corresponding bits set to 1. (Default = 0)
L2 Cache Data Memory Subsystem Lock. On allocations from the DM, avoid using the
ways that have the corresponding bits set to 1. (Default = 0)
Reserved.
L2 Cache Tag Clock Gating Enable. If set, the L2 tags would be clocked only when
accessed. Otherwise, the tags would be clocked whenever the bus controller clocks are
active. (Default = 0)
L2 Cache (always) Pass I/Os and MSRs. Reserved for Debug only. Pass I/Os and
MSRs through regardless of the state of the L2. (Default = 0)
L2 Cache Data Memory Subsystem Evictions (always) Dirty. Reserved for Debug
only. Treats all DM evictions as dirty. (Default = 0)
L2 Cache Wait for Data Memory Subsystem Writes. Reserved for debug only. Waits
for all data beats from DM before proceeding. (Default = 0)
L2 Cache Invalidate. Invalidate the entire contents of the L2 cache. This bit always
reads back as 0. (Default = 0)
L2 Cache Instruction Memory Subsystem Allocation Enable. A new IM access is
allocated into the L2 cache only if this bit is on. (Default = 1)
L2 Cache Data Memory Subsystem Allocation Enable. A new DM access is allocated
into the L2 cache only if this bit is on. (Default = 1)
L2 Cache Allocation Enable. A new line is allocated into the L2 cache only if this bit is
on (Default = 1)
L2 Cache Enable. If this bit is on, the arbiter redirects memory accesses to the L2 block.
(Default = 0)
L2_CONFIG_MSR Bit Descriptions
L2_CONFIG_MSR Register Map
L2_DM_LOCK
RSVD
RSVD
9
8
33234H
7
6
5
4
3
2
1
187
0