ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 309

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
63:38
31:6
Bit
37
36
35
34
33
32
5
4
3
2
1
0
Name
RSVD
CWD_CHECK_ERR
SYNCBUF_ERR
DFIFO_ERR
SMI_ERR
ADDR_ERR
TYPE_ERR
RSVD
CWD_CHECK_MSK
SYNCBUF_MSK
DFIFO_ERR_MASK
SMI_ERR_MASK
ADDR_ERR_MASK
TYPE_ERR_MASK
Description
Reserved. Set to 0.
Control Word Check Error. Reading a 1 indicates that an invalid control word was
read from the Display FIFO, which is indicative of a FIFO underrun. Writing a 1 to this
bit clears it.
Synchronizer Buffer Error. Reading a 1 indicates that the display pipe attempted to
read the synchronizer buffer while it was invalid. This is indicative of a synchronizer
buffer underrun. Writing a 1 to this bit clears it.
Display FIFO Underrun Error. Reading a 1 indicates that the asynchronous error
signal is being driven because the display FIFO has “run dry”. This implies that at
least one frame of the display was corrupted. Writing a 1 to this bit clears it; writing a
0 has no effect.
Uncleared SMI Error. Reading a 1 indicates that the asynchronous error signal is
being driven because a second SMI occurred while the first SMI went unserviced.
Unexpected Address Error. Reading a 1 indicates that the exception flag was set
because the DC received a GLIU0 transaction request.
Unexpected Type Error. Reading a 1 indicates that an asynchronous error has
occurred because the DC received a GLIU0 transaction with an undefined or unex-
pected type.
Reserved. Set to 0.
Control Word Check Error Mask. When set to 1, disables generation of the asyn-
chronous error signal when an invalid control word is read from the data FIFO.
Synchronizer Buffer Error Mask. When set to 1, disables generation of the asyn-
chronous error signal when invalid data is read from the synchronizer buffer.
Display FIFO Underrun Error Mask. When set to 1, disables generation of the asyn-
chronous error signal when at least one frame of the display was corrupted.
Uncleared SMI Error Mask. When set to 1, disables generation of the asynchronous
error signal when a second SMI occurred while the first SMI went unserviced.
Unexpected Address Error Mask. When set to 1, disables generation of an excep-
tion flag when the DC receives a GLIU0 request.
Unexpected Type Error Mask. When set to 1, disables generation of the asynchro-
nous error signal when the DC received a GLIU0 transaction with an undefined or
unexpected type.
GLD_MSR_ERROR Bit Descriptions
33234H
309