ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 460

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

460
15:14
Bit
18
17
16
13
12
11
10
9
8
7
INV VS POL
INV HS POL
UV SWAP
VSYNC SHFT
DIS DEC
601 MODE
VBI
RSVD
TASK
SGFR
SIGE
Name
33234H
Description
Invert VSYNC Polarity. Set to 1 to invert polarity of VSYNC (for 601 mode only).
Invert HSYNC Polarity. Set to 1 to invert polarity of HSYNC (for 601 mode only).
UV Swap.
0: No swap.
1: Swap lowest byte with next lowest byte in [23:0] input data stream. This is essentially
VSYNC Shift. This is the number of VOP clocks to shift the VSYNC with respect to
HSYNC for odd field detection in 601 mode.
00: Shift VSYNC earlier by 4 cycles (-4).
01: Shift VSYNC earlier by 2 cycles (-2).
10: Zero shift - both are aligned as they were received from Display Controller.
11: Shift later based on programmable value in DC Memory Offset 080h.
Disable Decimation. This is used in conjunction with 601 mode for 24-bit YUV/RGB out-
put on VOP.
Enable 601 Mode.
0: Disable.
1: Enable.
Vertical Blanking Interval. When this bit is set to 1, the Task bit (bit 9) is used to indi-
cate VBI data.
In BT.656 mode, the TASK bit (bit 9) in the EAV/SAV is fixed at 1, if this VBI bit is set,
then a value of 0 in the TASK bit location indicates VBI data.
In VIP 1.1 mode, the TASK bit in the EAV/SAV is defined such that 0 is VBI data, and 1 is
active video data. Therefore, this VBI bit has no effect in VIP 1.1 mode.
In VIP 2.0 mode, the TASK bit determines the value of the TASK bit in the EAV/SAV.
With the VBI bit set, the inverse of TASK indicates VBI data.
Reserved. Reads back as 0.
TASK. Value for the Task bit in VIP 2.0 mode.
Signature Free Run.
0: Disable. If this bit was previously set to 1, the signature process will stop at the end of
1: Enable. If SIGE (bit 7) is set to 1, the signature register captures data continuously
Signature Enable.
0: Disable. VP Memory Offset 808h[31:0] is reset to 0000_0000h and held (no capture).
1: Enable. The next falling edge of VSYNC is counted as at the start of the frame to be
If the SGFR bit (bit 8) is set to 1, the signature register captures the pixel data signature
continuously across multiple frames.
If SGFR is cleared to 0, a signature is captured for one frame at a time, starting from the
next falling VSYNC.
After a signature capture is complete, VP Memory Offset 808h[31:0] can be read to
determine the CRC check status. Then proceed to reset the SIGE which initializes VP
Memory Offset 808h[31:0] as an essential preparation for the next round of CRC checks.
swapping the U and V, and if in RGB, swapping G and B.
the current frame.
across multiple frames.
used for CRC checking with each pixel clock beginning with the next VSYNC.
VOP_CONFIG
Bit Descriptions (Continued)
AMD Geode™ LX Processors Data Book
Video Processor Register Descriptions